International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 6, June 2012) 292 FPGA Implementation of Different Multiplier Architectures Laxman S, Darshan Prabhu R, Mahesh S Shetty ,Mrs. Manjula BM, Dr. Chirag Sharma NMIT, Bangalore,Govindapura,Gollahalli NMIT, Bangalore,Govindapura,Gollahalli NMIT, Bangalore,Govindapura,Gollahalli Abstract-In this paper 2 different multiplier architectures are implemented in Xilink FPGA and compared for their performance. Here these architectures are implemented for 4,8,16 bit Based on various speed- up schemes for binary multiplication, a comprehensive overview of different multiplier architectures are given in this report. In addition , it is found that booth multiplier is faster than array multiplier. I. INTRODUCTION Multiplication is one of the basic functions used in digital signal processing (DSP). It requires more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all instructions in a typical processing unit is multiplier. The multiplier is a fairly large block of a computing system. The amount of circuitry involved is directly proportional to square of its resolution i.e., a multiplier of size of n bits has O (n 2 ) gates. . This paper presents various multiplier architectures. Multiplier architectures fall generally into two categories i.e., “tree” multipliers and “array” multipliers. Tree multipliers add as many partial products in parallel as possible and therefore, are very high performance architectures. II. OBJECTIVES AND TOOLS USED Project objectives: The main objective of this project is design and implementation of Array and Booth multiplier for different bit sizes. Tools used: Simulation Software: ISE 9.2i is used for design and implementation and ModelSim 6.1e is used for modeling and simulation. Hardware used: Xilinx vertex 2p (Family), XC2VP30 (Device), FG (Package) FPGA device. III. TYPES OF MULTIPLIER Array multiplier Multiplication is a mathematical operation that at its simplest is an abbreviated process of adding an integer to itself a specified number of times. . Multiplication involves three main steps:  Partial product generation  Partial product reduction  Final addition For the multiplication of an n-bit multiplicand with an m- bit multiplier, m partial products are generated and product formed is n + m bits long. To perform N -bit by N-bit multiplication the N-bit multiplicand A is multiplied by N-bit multiplier B to produce product. The unsigned binary numbers A and B can be expressed as: A = ........(1) B = ----(2)