From FinFET to Nanowire ISFET Michal Zaborowski, Daniel Tomaszewski, Piotr Dumania, Piotr Grabiec Division of Silicon Microsystem and Nanostructure Technology Institute of Electron Technology ITE Warsaw, Poland e-mail: mzab@ite.waw.pl Abstract— A p-type FinFET manufacturing process has been presented. It is a starting point for development of H + ion- sensitive n-type nanowire FETs (ISFETs). In the paper, new process steps are pointed out together with SEM examination. Characteristics of the n-type junctionless FETs have been measured in buffer solutions in a beaker and in contact with a single drop of the liquid. ISFET current versus pH and voltage versus pH curves have been presented and discussed. Relatively small hysteresis and drifts in pH measurements have been found. I. INTRODUCTION Multi-gate MOSFETs exhibit a number of advantages as compared to single-gate ones [1]. Because of a good gate control over channel conduction they are predestined for low- voltage applications. FinFETs are good candidates for 22nm technology and beyond [2]. Obviously, manufacturing of such devices is based on sophisticated photolithography and plasma patterning processes. Such techniques allowing for large volume fabrication of ultra-low size devices are available only for large companies. In the small laboratory case an electronolithography-based manufacturing of FinFETs is possible, but it allows in reality only for a very small scale processing. In ITE clean-room a smart technique for fabrication of near 100 nm silicon Fins has been developed, which in some sense remains within the gap between the two approaches mentioned above, and expressed in terms of productivity. The resulting FinFET devices are briefly described and characterized in the next chapter. Semiconductor sensors seem to be among the most interesting areas of application of the Fin transistors [3]. The Si-Fin that is fixed only at the bottom to BOX layer can be considered as a nanowire (NW). Its conductance can be controlled by potential of a surrounding liquid analyte. Development of the fabrication process toward H + ion- sensitive FET (ISFET) has been the aim of the work. II. FINFET DEVICE FABRICATION P-type FinFETs have been fabricated in p SOI wafers, which have been doped with phosphorus ions to change the wafers into n type. Two hundred nanometer wide and narrower Si Fins have been prepared using a PaDEOx technique [4,5]. In this technique, the SOI Fins are plasma etched in Bosch process with use of SiO 2 hard mask. Width of the mask is process controlled. The mask originates from short range lateral thermal oxidation of silicon along an edge of nitride pattern. Length of the Fins is controlled by standard 365 nm lithography. Next a gate thermal oxide and poly-Si gate electrode have been grown over the Fins. This part of the flow chart is presented in the left column of Table 1. The FinFETs have been covered with PSG/SiO 2 passivation layer. Then contact holes have been patterned and Ti:W/Al metallization has been done by magnetron sputtering step. The details of the Fin and poly-Si gate are shown in Fig.1. In the experiment described above the double-Fin p-channel FinFETs with different channel drawn lengths have been manufactured, namely 2.5, 3.0 and 6.0 μm. They have been used as a reference for further experiments. Their electrical characterization has been done using a set-up consisting of Keithley 2600A series SMUs,. Within the characterization task the measurements of output and input I-V characteristics have been done. In Fig. 2a a family of I DS -V DS curves of the FinFET with the channel length L=6.0 μm is shown. The device exhibits a correct behavior typical for long-channel devices. In Fig. 2b a set of I DS -V GS curves of the FinFETs (L=6.0 μm) is shown. TABLE I. COMPARISON OF THE FINFET AND ISFET PROCESSES FinFET Processes ISFET Processes A Gate oxidation A Gate oxidation B Poly-Si deposition B Gate nitride LPCVD C Gate photolithography C Contact photolithography D Poly-Si plasma etching D Nitride plasma etching E Passivation PSG/oxide CVD E Oxide wet etching F Contact photolithography F Metal PVD G Contact etching plasma/wet G Metal photolithography and etching H Metal PVD H Passivation oxide CVD I Metal photolithography and etching I Active and bond areas photolithography J Oxide wet etching The work was partially supported by the Ministry of Science and High Education in Poland under grant NRO2 0010 06/2009. 978-1-4673-1708-5/12/$31.00 ©2012 IEEE 165