Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays ⋆ John Karro 1 and James Cohoon 2 1 Computer Science Program, Oberlin College, Oberlin, OH 44017 john.karro@oberlin.edu 2 Department of Computer Science, University of Virginia, Charlottesville, VA 22903 cohoon@virginia.edu Abstract. In this paper we present a new method of integrating the placement and routing stages in the physical design of channel-based ar- chitectures, and present the first implementation of this method: Gambit. Based on a graph coloring representation of the routing problem, we are able to produce circuit placements and detailed routes simultaneously, allowing routing constraints to influence decisions made in creating the placement. Gambit produces circuit mappings for both standard and three-dimensional FPGA architectures, and serves primarily as a proof- of-concept: the proposed algorithm will simultaneously perform place- ment and detailed routing for channel-based architectures. While the quality of Gambit mappings are not yet competitive with state-of-the- art tools in the literature, experimental results indicate that it does have the potential to become so. 1 Introduction Given an abstract description of a circuit, it is no easy task to physically imple- ment that description in hardware. The designer must map each of the compo- nents to a location on the chip, and then must run wires between component to provide the proper connections. All of this must be done with an eye towards keeping connections as small as possible, and towards minimizing the amount of chip area required for the design. The problems involved in finding an opti- mal solution are NP-complete, and researchers are continually developing new heuristics to produce high-quality solutions in a reasonable amount of time. The task of physical design is frequently divided into several stages. For the popular FPGA architecture these include technology mapping, placement, global routing and detailed routing. Traditionally these have been performed in sequence, with the output of each becoming the input of the next. While such a division reduces the complexity of the problem, it has been argued that solving ⋆ Research supported by theVirginia Aerospace Consortium Graduate Fellowship Pro- gram, the National Science Foundation under grants CDA 9634333, CDR 9224789, MIP 9107717, DUE 9554715, and DUE 9653413, and by the Department of Com- puter Science at the University of Virginia. G. Brebner and R. Woods (Eds.): FPL 2001, LNCS 2147, pp. 243–253, 2001. c  Springer-Verlag Berlin Heidelberg 2001