96 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 1, FEBRUARY 2015 Scratching of Patterned Cu/Dielectric Surface Layers by Pad Asperities in CMP Sanha Kim, Nannaji Saka, and Jung-Hoon Chun Abstract—In chemical-mechanical polishing (CMP), as the rough polymer pad slides over patterned structures of metal interconnects and dielectrics the pad asperities themselves, though soft, may scratch the relatively hard layers. The fully plastically deformed pad asperities with high interfacial fric- tion are the primary sources of pad scratching. In this paper, scratching of Cu/dielectric line structures by pad asperities is investigated. First, the scratching criteria and the scratch-regime maps, constructed previously for monolithic layers based on con- tact mechanics are extended for the patterned layers. Then sliding experiments have been conducted on patterned Cu/dielectric sur- face layers of various linewidths using solid polymeric pins loaded into the fully plastically deformed state, as well as commercial CMP pads. Specifically, the role of the width of Cu and dielec- tric lines in comparison with the contact diameter is examined. The theoretical models predict that the scratch criteria for pat- terns with wide lines are the same as those for monolithic layers, whereas patterns with extremely narrow lines behave as com- posite layers with effective mechanical properties. Experimental results validate the scratch criteria based on contact mechanics. Index Terms—Semiconductor, defect, CMP. I. I NTRODUCTION I N THE manufacture of ultra large-scale integrated (ULSI) circuits and micro-electromechanical systems (MEMS), the chemical-mechanical polishing (CMP) process is widely employed for producing extremely smooth and flat surfaces of patterned structures comprising diverse materials [1]–[3]. While the CMP process has been continuously optimized over decades, such defects as micro- and nano-scale scratches are invariably generated on the surfaces being polished. These scratches or defects cause serious problems in subsequent processing [4]. Due to the usage of low-k, low-strength dielectrics in recent years, moreover, the propensity for scratch generation has greatly increased [5], [6]. It is generally believed that the larger agglomerated abrasive particles primarily scratch the surface being polished [7]–[11]. It has been reported, moreover, that scratches can also be gen- erated when the CMP pads are slid over the Cu layers without any abrasive particles [12], [13]. Recent research has shown that even the softer polymeric pad asperities may, under certain Manuscript received July 11, 2014; revised September 29, 2014; accepted November 21, 2014. Date of publication November 25, 2014; date of cur- rent version January 30, 2015. This work was supported by the Samsung Electronics Corporation. The authors are with the Laboratory for Manufacturing and Productivity, Massachusetts Institute of Technology, Cambridge, MA 02139 USA (e-mail: sanhkim@mit.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TSM.2014.2375672 Fig. 1. Schematic of contact between a random, rough pad, and a smooth flat surface layer. conditions, generate scratches on the relatively hard surface layers. Based on the theoretical and experimental work on monolithic layers, it has been found that scratching by pad asperities strongly depends on the pad-to-layer hardness ratio and the interfacial friction between the pad asperities and the surface layers [13]–[16]. In the present study, scratching by pad asperities on pat- terned Cu/dielectric layers is investigated by contact mechan- ics models, and by experiments using solid polymer pins and polishing pads. In addition to the mechanical properties of the pad asperities and layer materials and the friction between the surfaces considered earlier, the effects of pattern geometry on scratching are specifically investigated. The results of sliding experiments using solid polymer pins and CMP pads on pat- terned layers of various linewidths qualitatively validate the theoretical predictions. II. THEORY OF SCRATCHING OF I NTERCONNECTS AND DIELECTRICS BY CMP PADS In comparison with the surfaces being polished, typical CMP pads are rough. The asperity height distribution of the pads is known to be either Gaussian or exponential [17], [18]. As the rough polishing pad is pressed against a smooth, flat layer at nominal pressures 7 -35 kPa (1 - 5 psi), the real area of contact is about a percent or less of the nominal area, Fig. 1 [19]–[21]. Asperities of height z a less than the separa- tion distance d (z a < d) do not contact the surface layer, and only the tall asperities (z a ≥ d) will be in contact. The applied pressure, therefore, is concentrated at the asperity contacts, and will be much greater than the nominal pressure. Moreover, among those asperities that are in contact, the contact pressure may be even higher at a few tallest asperities that deform the greatest. Fig. 2(b)–(e) are schematics of the different asperity defor- mation modes and surface tractions at the asperity contact, as a function of the approach distance δ (= z a - d). If δ<δ y , 0894-6507 c  2014 IEEE. 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