660 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO.5, MAY 2011 Development of Large Die Fine-Pitch Cu/low- FCBGA Package with through Silicon via (TSV) Interposer Tai Chong Chai, Xiaowu Zhang, John H.Lau,Cheryl S. Selvanayagam, Pinjala Damaruganath, Yen Yi Germaine Hoe, Yue Ying Ong, Vempati Srinivas Rao, Eva Wai, Hong Yu Li, E. Bin Liao, Nagarajan Ranganathan, Kripesh Vaidyanathan, Shiguo Liu, Member, IEEE,Jiangyan Sun, Mullapudi Ravi, Charles J. Vath,III, Member, IEEE,and Yoshihiro Tsutsumi Abstract— The continuous pushfor smallerbumppitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnec- tion.However, theconventional organicbuildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip thatis vulnerable to thermal-mechanical stressand improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-µm SnAg bump pitch oftotal11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of Manuscript received May 21, 2009;revised March 4, 2010;accepted July 22, 2010. Date of current version June 2, 2011. Recommended for publication by Associate Editor K.-N. Chiang upon evaluation of reviewers’ comments. T. C. Chai, X. Zhang, C. S. Selvanayagam, P. Damaruganath, Y. Y. G. Hoe, Y. Y. Ong,V. S. Rao,E. Wai,H. Y. Li, E. B. Liao,N. Ranganathan, and K. Vaidyanathan are with theDepartment of Microsystems Modulesand Components, Institute of Microelectronics, Agency for Science, Technology and Research,117685,Singapore(e-mail: taichong@ime.a-star.edu.sg; xiaowu@ime.a-star.edu.sg; Cheryl@ime.a-star.edu.sg; pinjala@ime.a-star.edu. sg; hoeyy@ime.a-star.edu.sg; ongyy@ime.a-star.edu.sg; vempati@ime.a- star.edu.sg; wailc@ime.a-star.edu.sg; lihy@ime.a-star.edu.sg; ebin@ime.a- star.edu.sg; Nathan@ime.a-star.edu.sg; Kripesh@ime.a-star.edu.sg). J. H. Lau is with the Electronics & Optoelectronics Laboratory, Indus- trialTechnology Research Institute, Hsinchu 310, Taiwan (e-mail: john- lau@itri.org.tw). S. Liu is with the IBIDEN Singapore Pte Ltd., 339773, Singapore (e-mail: liu.isp@ibiden.com). J. Sun is with the Shanghai Sinyang Semiconductor Materials Company, Ltd.,Shanghai 201616, China (e-mail: jiangyan_sun@sinyang.com.cn). M. Ravi is with the Tango Systems, Inc., San Jose, CA 95131 USA (e-mail: rmullapudi@tangosystemsinc.com). C. J. Vath is with ASM Technology Singapore Pte Ltd., 768924, Singapore (e-mail:vathcj@singnet.com.sg). Y. Tsutsumi is with DISCO Hi-Tec Pte Ltd., 417938, Singapore (e-mail: Tsutsumi@disco.co.jp). Colorversions of one ormore ofthe figures in this paper are available online at http://ieeexplore.ieee.org. DigitalObjectIdentifier 10.1109/TCPMT.2010.2101911 the large die mounted on TSV interposer with Pb-free solde bumps and underfill have been set up. The FCBGA samples passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy resistance measurements. Index Terms— Cu/low-k chip, mechanical modeling, packag- ing assembly, reliability, thermal modeling, through silicon via interposer, wafer fabrication. I. INTRODUCTION F LIP CHIP packagingwith the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring as the interconnect density is continuing to shrink an the cost of fabricating finer pitch organic substrate is increa significantly. To address these needs, through silicon via (TS interposer has emerged as a good solution to provide high wiring density interconnection, minimizing coefficient of the mal expansion (CTE) mismatch between the Cu/low- k die an the copper-filled TSV interposer, and improving electrical p formance due to shorter interconnection from the chip to th substrate. In the literature, IBM [1]–[4]designed, fabricated, and characterized silicon carrier on ceramics packages, including silicon through-vias, multiple levels of back end of line wirin high-I/O interconnection, and high-I/O test probe structures at 50 µm pitch.Thermo-mechanical stress analysis on the TSV structure due to differential thermal expansion during manufacturing process of via and inter-level dielectric (ILD) levels were conducted with via chain structure under tempe ature cycling testing. Tungsten-filled via was considered for reducing the thermo-mechanical mismatch between standard Cu-filled via and silicon. Both System Fabrication Technolo- gies, Inc. [5] and Shinko Electric Industries Company, Ltd. [ developed a silicon interposer with TSV and fine multilayer wiring. The silicon interposer size is 11 mm × 11 mm. The chip size used is 3.35 mm × 3.1 mm. A test module consistin of a chip-on-silicon interposer with TSV was fabricated and tested under various reliability tests, and no major problem was reported. However, their initial study with chemical vap deposition silicon dioxide (SiO 2 ) as interlayer dielectric at the top region of Cu-TSV was found to crack after reflow preconditioning at 245 °C, but subsequently the problem was overcome by using polymer as ILD materials. Samsung 2156–3950/$26.00 © 2011 IEEE