72 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 33,NO. 1,FEBRUARY 2010 Fine-Pitch Capabilities of the Flat Ultra-Thin Chip Packaging (UTCP) Technology Jonathan Govaerts, Erwin Bosman, Wim Christiaens, and Jan Vanfleteren, Member, IEEE Abstract—This paper describes the fine-pitch interconnection capabilities of the ultra-thin chip packaging (UTCP) technology, a technology under development for embedding thin chips in a flexible polyimide (PI) substrate. It allows for fully flexible elec- tronics, as the rigid chips are thinned down to 20–30 , at which point they become truly flexible themselves. This way, instead of just a flexible substrate with rigid components assembled on top, the entire circuitry can be incorporated inside a 30–40 thin chip package. The paper briefly introduces the technology’s background with a short description of the fabrication process. Building on the developments already achieved, some further optimizations are discussed, and the technology is tested for its fine-pitch interconnection capabilities using test chips with four-point probe and daisy chain patterns, with a pitch down to 40 . The possibility to package several chips in the same substrate is investigated, as well, and finally an outlook on future experiments is briefly discussed. Index Terms—Chip embedding, fine-pitch interconnection, flex- ible polyimide substrates, thin chip packaging. I. INTRODUCTION T HESE DAYS, there is a lot of interest in making electronic devices as light and compact as possible, as the electronics market is rapidly expanding with all sorts of portable devices for everyday use. In this view, flexible substrates are often an in- teresting alternative for rigid printed circuit boards (PCBs) be- cause they are light and conformable, especially an advantage when integrating electronic devices for wearable applications. A light and flexible substrate by itself however does not guar- antee a light and flexible end result. The flexibility is often dras- tically reduced when rigid components are assembled onto the substrate. Thus, considering the current trend of increasing component density, which is of course welcomed for wearable devices, the benefit of the flexibility of the substrate is more and more over- shadowed by the rigidity of the components. An obvious way of tackling this issue is to use smaller and thinner, and conse- quently also lighter, components. Manuscript received September 08, 2008; revised February 17, 2009. First published June 12, 2009; current version published February 26, 2010. This work was supported by the European Union through the programs FlexiDis under Contract IST-004354 and SHIFT under Contract IST-507745. This work was recommended for publication by Associate Editor R. Mahajan upon evalu- ation of the reviewers’ comments. The authors are with the Centre for Microsystems Technology (CMST), IMEC, B-3001 Leuven, Belgium, and also with the Department of Electronics and Information Systems (ELIS), Ghent University, B-9000 Ghent, Belgium (e-mail: jonathan.govaerts@UGent.be). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TADVP.2009.2018134 Fig. 1. Process flow for the flat UTCP technology used. However, when chips are thinned down to approximately 20 , they are too fragile to be assembled onto a substrate with standard die assembly techniques (at present). Recently, a technology for embedding such thin chips in flexible substrates has been developed at IMEC [1]. This technology embeds these fragile ultra-thin chips in spin-on polyimide (PI) substrates, and is therefore called ultra-thin chip packaging (UTCP). It offers the possibility of reducing weight, while at the same time enhancing the mechanical flexibility of the electronic circuitry. II. FLAT UTCP TECHNOLOGY DESCRIPTION The technology used here is an enhanced version of IMEC’s first UTCP technology with an updated process flow to realize a more symmetrical package. The process flow used is depicted in Fig. 1. The base PI layer is spincoated onto a rigid (glass) carrier substrate and cured. Then, the photodefinable PI is spincoated, illuminated through a mask, and developed to define the chip cavity. After curing, the chip is placed face up, using BCB in the cavity as adhesive. The BCB is cured, and the top layer of PI is spincoated and cured in the same way as the base PI layer (thus creating a symmetrical substrate sandwich). The via holes to the chip contacts are laser drilled and after the metal pattern is realized on top, the substrate can be released from its carrier. The fabrication process for this technology has been de- scribed extensively in [2], together with the first electrical results for the coarser interconnect pitch patterns. III. TEST CHIPS’DESCRIPTION The chips used for the embedding trials are thinned-down test chips available at IMEC. They are specified as PTCK chips, which stands for “Packaging Test Chip version K,” and measure 5 mm 5 mm. There are four different versions of PTCKs, but 1521-3323/$26.00 © 2010 IEEE