Graphene Synthesis on Cubic SiC/Si Wafers. Perspectives for Mass Production of Graphene-Based Electronic Devices Victor Yu. Aristov,* ,†,‡ Grzegorz Urbanik, † Kurt Kummer, § Denis V. Vyalikh, § Olga V. Molodtsova, † Alexei B. Preobrajenski, | Alexei A. Zakharov, | Christian Hess, † Torben Ha ¨nke, † Bernd Bu ¨ chner, † Ivana Vobornik, ⊥ Jun Fujii, ⊥ Giancarlo Panaccione, ⊥ Yuri A. Ossipyan, ‡ and Martin Knupfer † † Leibniz Institute for Solid State and Materials Research, D-01069 Dresden, Germany, ‡ Institute of Solid State Physics, Russian Academy of Sciences, Chernogolovka, Moscow District, 142432, Russia, § Institute of Solid State Physics, Dresden University of Technology, D-01062 Dresden, Germany, | MAX-lab, Lund University, Box 118, 22100 Lund, Sweden, and ⊥ TASC National Laboratory, INFM-CNR, SS 14, km 163.5, I-34012 Trieste, Italy ABSTRACT The outstanding properties of graphene, a single graphite layer, render it a top candidate for substituting silicon in future electronic devices. The so far exploited synthesis approaches, however, require conditions typically achieved in specialized laboratories and result in graphene sheets whose electronic properties are often altered by interactions with substrate materials. The development of graphene-based technologies requires an economical fabrication method compatible with mass production. Here we demonstrate for the fist time the feasibility of graphene synthesis on commercially available cubic SiC/Si substrates of >300 mm in diameter, which result in graphene flakes electronically decoupled from the substrate. After optimization of the preparation procedure, the proposed synthesis method can represent a further big step toward graphene-based electronic technologies. KEYWORDS Graphene layer, synthesis, cubic SiC surface G raphene possesses astonishing electronic properties, 1,2 like the exceedingly high charge carrier mobility and the occurrence of Dirac fermions. 3-6 The unique elec- tronic properties of graphene make this material an interesting one for potential applications in electronic devices. 7-9 His- torically the first method of graphene fabrication involved handmade processes such as mechanical exfoliation 1,10 and was not practical. Other methods are based on graphene films grown on different substrates. The self-organized growth of carbon atoms into the graphene structure is highly favored on substrates with comparable lattice structure. This was demonstrated for instance for graphene grown on the Ni(111) or Ir(111) surfaces 11 and for graphene on the hexagonal 6H- and 4C- SiC(0001) (R-SiC) surfaces. 12-14 The preparation of graphene layers by the thermal decomposition of R-SiC has been proposed as a promising method for the synthesis of homo- geneous, wafer-size graphene layers for technological ap- plications. The method has considerable advantage due to the fact that R-SiC is a large gap semiconductor, which serves as a substrate for the graphene layer. The substrate considered in this paper, cubic 3C-SiC (- SiC) is readily grown in large size (>300 mm in diameter) commercially available Si wafers. 15-17 Apparently, due to its cubic lattice, -SiC does not appear suitable for graphene growth. Contrary to common belief, we succeeded in grow- ing high-quality graphene on cubic -SiC and found that the interaction with the substrate is almost negligible, rendering this system a perfect candidate for future graphene-based electronics. Bulk -SiC has zinc blende (sphalerite) structure, i.e., its lattice is composed of two face-centered sublattices shifted with respect to the other in the direction of the cube’s diagonal by one-quarter of the diagonal length. Since one sublattice contains silicon atoms and the other carbon atoms, the crystal can be considered as composed of mona- tomic Si and C planes alternating in the [001] direction. Consequently the (001) surface is either silicon or carbon terminated. We exposed our sample with a Si-rich surface to a series of annealing cycles with increasing temperature from 1200 K up to 1550 K. Over this process, all known SiC(001) surface reconstructions 18-20 were observed in the low- energy electron diffraction (LEED) patterns. We show in Figure 1a the C 1s photoemission (PE) spectra taken at hν ) 400 eV photon energy from the Si-rich -SiC(001) 3 × 2 surface, the C-terminated -SiC(001) c(2 × 2) surface and the C-rich -SiC(001) 1 × 1 surface. In the case of the Si-rich surface, all carbon atoms occupy equivalent bulk sites. Hence only one component at 282.9 eV binding energy (BE) is present in the PE spectra. Surface * To whom correspondence should be addressed: e-mail, V.Aristov@ ifw-dresden.de; phone, +493514659548. Received for review: 12/12/2009 Published on Web: 00/00/0000 pubs.acs.org/NanoLett © XXXX American Chemical Society A DOI: 10.1021/nl904115h | Nano Lett. XXXX, xxx, 000–000