Journal of Alloys and Compounds 382 (2004) 24–28 Transmission electron microscopy of iridium silicide contacts for advanced MOSFET structures with Schottky source and drain A. Laszcz a , J. K˛ atcki a,∗ , J. Ratajczak a , G. Larrieu b , E. Dubois b , X. Wallart b a Institute of Electron Technology, Al. Lotników 32/46, 02-668 Warsaw, Poland b IEMN/ISEN, UMRS CNRS 8520, Avenue Poincare, Cite Scientifique, BP 69, 59652 Villeneuve d’Ascq Cedex, France Received 15 September 2003; received in revised form 15 March 2004; accepted 25 March 2004 Abstract The IrSi x contacts have been used in Accumulated Low Schottky Barrier MOSFET on SOI. An IrSi x layer is formed as a result of reaction between metal and semiconductor during annealing. The process of silicidation in the Ir/Si/SiO 2 /Si structure has been studied by means of cross-sectional transmission electron microscopy (XTEM). The influence of annealing temperatures (300, 600, 900 ◦ C) on silicide formation was analysed. The formation of a thin IrSi x layer was observed at a temperature as low as 300 ◦ C. In the Ir/Si/SiO 2 /Si structure annealed at 600 ◦ C, the Ir atoms are shown to penetrate across the Si layer, causing disturbance of the Ir/Si interface. After annealing at 900 ◦ C large IrSi x islands were formed in Si. The expansion of the IrSi x grains in the Si layer was observed. TEM results were correlated with XPS and electrical measurements. © 2004 Elsevier B.V. All rights reserved. Keywords: Transmission electron microscopy; Photoelectron spectroscopy; Semiconductors; Surfaces and interfaces; Thin films 1. Introduction In a good accumulated low Schottky barrier-SOI-MOSFET device, the source/drain (S/D) contacts should have a very high barrier to the substrate to reduce leakage current whereas a very low barrier height to the inverted channel to have an unimpeded drain current [1]. In order to alleviate these two conflicting constraints on the barrier height, a thin silicon-on-insulator (SOI) substrate can be judiciously used to eliminate the first requirement [2]. In this context, IrSi-based metallic S/D junctions appear as a very competi- tive candidate because this silicide demonstrates the lowest known Schottky barrier to holes [3] potentially even more attractive than PtSi-based contacts for the integration of PMOS transistors [2,4]. The Ir–Si phases are formed when Ir is deposited on Si and silicided by subsequent annealing [5]. Petersson et al. [6] reported that at annealing temperatures: 400–600 ◦ C, 500–950 ◦ C and 1000 ◦ C IrSi, IrSi 1.75 and IrSi 3 phases were formed, respectively. The another compositions of the Ir–Si phase, such as Ir 3 Si 5 and Ir 3 Si 4 (formed in ultrahigh vac- ∗ Corresponding author. Fax: +48-22-847-0631. E-mail address: katcki@ite.waw.pl (J. K˛ atcki). uum) have been found by Engström et al. [7] and by Chung and Hwang [8]. One of important issues is the influence of the Schot- tky barrier contact microstructure on its electrical proper- ties. The differences in Schottky barrier heights depend on phase composition and microstructures of the Ir–Si system [5,9–11]. TEM investigation is very important for technol- ogy optimization and understanding the electrical perfor- mance of Schottky contact. The aim of this paper is the investigation of the influence of the annealing temperature on silicidation process in the Ir/Si/SiO 2 contact structure to p-type Si by means of trans- mission electron microscopy (TEM). Results of TEM ob- servations have been correlated to XPS and electrical mea- surements. 2. Experimental The Ir layer was deposited by means of e-gun evapo- ration on the SOI structure. The thicknesses of the Ir, Si and SiO 2 layers were 15, 100 and 400nm, respectively. In order to form Schottky contacts the samples were an- nealed by rapid-thermal-annealing (RTA) process at follow- 0925-8388/$ – see front matter © 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.jallcom.2004.03.145