Mechanism of positive charge generation in the bulk of HfAlO/SiO 2 stack Piyas Samanta a,b , Chin-Lung Cheng c, * , Yao-Jen Lee d , Mansun Chan b a Physics Department, Vidyasagar College for Women, Kolkata 700 006, 39 Sankar Ghosh Lane, India b Dept.of Electronic and Computer Engg., Hong Kong University of Science and Technology, Kowloon,Hong Kong c Institute of Mechanical and Electro-Mechanical Engineering, National Formosa University, Yunlin,Taiwan 63201, ROC d National Nano Device Laboratories, Hsinchu,Taiwan,ROC a r t i c l e i n f o Article history: Received 3 March 2009 Accepted 3 March 2009 Available online 9 March 2009 Keywords: Positive charge generation HfAlO/SiO 2 stacked dielectric Stress-induced positive charge Metal–oxide–semiconductor Reliability a b s t r a c t We have investigated electrical stress-induced positive charge buildup in a hafnium aluminate (HfAlO)/ silicon dioxide (SiO 2 ) dielectric stack (equivalent oxide thickness = 2.63 nm) in metal–oxide–semicon- ductor (MOS) capacitor structures with negative bias on the TaN gate. Various mechanisms of positive charge generation in the dielectric have been theoretically studied. Although, anode hole injection (AHI) and valence band hole tunneling are energetically favorable in the stress voltage range studied, the measurement results can be best explained by the dispersive proton transport model. Ó 2009 Elsevier B.V. All rights reserved. 1. Introduction Positive charge buildup in the interfacial SiO 2 layer during elec- trical stress of MOS capacitors with Hf based high- j dielectric stack is an experimentally established fact [1–7]. However, the origin of the positive oxide charge remains controversial between holes [3– 5] and proton-related defects [6,7]. Therefore,the present work is an attempt to resolve the above controversy with an aim to gain better physicalinsights on the generation mechanism(s)of the stress-induced positive charges in the bulk of the dielectric during negative bias constant voltage stress (CVS). 2. Experimental Devices studied here were nMOS capacitors with TaN gate on HfAlO (2.0 nm)/SiO 2 (2.0 nm) stack on (1 0 0) oriented boron doped silicon wafers of 1525 X cm resistivity. The HfAlO films were deposited from a HfO 2 Al 2 O 3 combination with 1:1 weight ratio by ALD technique. Further details of device fabrication can be found elsewhere [2].DC stress and sensing measurements were done at room temperature in a dark shielded chamber on several identical test structures. A 2.63 nm of the EOT (t eq ) of the gate stack was estimated from full quantum mechanical (QM) simulation of the measured 100 kHz CV results. 3. Results and analysis In our devices, high-frequency CV curves shifted towards more negative voltage after CVS as depicted in Fig. 1a, indicating positive charge buildup close to the Si/SiO 2 interface [1,2].Positive oxide charge buildup was further confirmed (Fig. 1b) from the negative shift D V mg of the midgap voltage after electrical stress relative to the fresh device according to [1] D N ot ¼ D V mg e ox q t eq ; ð1Þ where q is the magnitude of electron charge, e ox is the permittivity of SiO 2 and t eq is the EOT of the stack and D N ot is the variation of oxide trapped charge density relative to the fresh device. Fig. 2 shows the variations in the density of positive charge buildup D N þ ot as a function of stress time during CVS at various stress volt- ages.Zero field detrapping of oxide trapped positive charge is also studied as illustrated in Fig. 3. The straight line nature of the midgap voltage shift D V mg because ofself detrapping versus logarithmic relaxation time s r as shown in Fig. 3a indicates the existence of tunnel detrapping [8] of bulk positive oxide charges at room temperature. Tunnel detrapping of positive oxide charge is physically conformity with detrapping of trapped holes from the as-fabricated traps at room temperature.Therefore,it seems that hole trapping may explain the observed positive oxide charge buildup in the high- j stack.A plot of instantaneous zero field emission rate of trapped positive oxide charge versus reciprocalof detrapping time s r yielded a straight line as evident from Fig. 3b. This means that intrinsic hole 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.03.002 * Corresponding author.Tel.: +886 5 6315396; fax: +886 5 6315397. E-mail addresses: piyassamanta@yahoo.co.in (P. Samanta), chengcl@nfu.edu.tw (C.-L. Cheng). Microelectronic Engineering 86 (2009) 1767–1770 Contents lists available at ScienceDirect Microelectronic Engineering j o u r n a l homepage: w w w . e l s e v i e r . c o m / l o c a t e / m e e