994 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006 Sensorless Optimization of Dead Times in DC–DC Converters With Synchronous Rectifiers Vahid Yousefzadeh, Student Member, IEEE, and Dragan Maksimovic ´ , Member, IEEE Abstract—This paper introduces an approach to achieve op- timum dead times in dc–dc converters with synchronous rectifiers without sensing any of the power-stage signals other than the output voltage. The dead times are adjusted adaptively to mini- mize the duty-cycle command, which results in maximization of the converter efficiency. The method is particularly well suited for digital controller implementation, requiring no additional analog components or modifications of standard gate-drive circuitry. Experimental results for a digitally controlled 5 V-to-1 V, 5-A syn- chronous buck converter demonstrate practical implementation of the sensorless dead-time optimization algorithm. Index Terms—DC–DC converter, dead time, synchronous recti- fier, sensorless. I. INTRODUCTION B ECAUSE of significantly lower conduction losses, synchronous rectifiers are now used in essentially all low-voltage dc power supplies including converters for battery-operated electronics, point-of-load converters, micro- processor power supplies, etc. As an example, Fig. 1 shows a synchronous buck dc–dc converter, and Fig. 2 shows typical experimental waveforms. It is well known that optimum utiliza- tion of a synchronous rectifier depends on the ability to adjust the commutation dead-times and . Too long dead times (as shown in Fig. 2) result in additional losses due to the body diode conduction and the body-diode reverse recovery. Too short (or negative) dead-times may result in simultaneous conduction of the main switch and the synchronous recti- fier , with even more adverse penalties in the converter effi- ciency. Various gate-drive schemes have been proposed to ad- dress the synchronous rectifier commutation. In the presence of parameter tolerances, temperature variations and operating point changes, the simplest approach of fixed dead times often yields severely degraded efficiency, especially in converters op- erating at relatively high switching frequencies (in the hundreds of kHz to MHz range) [1]. Previously proposed schemes for improved synchronous rec- tifier commutation have been based on the idea that the syn- chronous rectifier should switch as an ideal rectifier: it should be turned on exactly at the time when the voltage across it drops to zero, and it should be turned off exactly at the time when the current through it drops to zero [2]. Direct implementation Manuscript received January 14, 2005; revised September 15, 2005. This work was supported by Toshiba through the Colorado Power Electronics Center. Recommended by Associate Editor B. Lehman. V. Yousefzadeh is with the Colorado Power Electronics Center, Electrical and Computer Engineering Department, University of Colorado, Boulder, CO 80309 USA (e-mail: yousefza@colorado.edu; maksimov@colorado.edu). Digital Object Identifier 10.1109/TPEL.2006.876850 Fig. 1. Synchronous buck converter proof-of-concept prototype: 5 V, 1V,0 5 A, 4.3 H, 705 F, 200 kHz, MOSFETs: Si4888DY. Fig. 2. Experimental waveforms for 2.5 A; the dead times are too long. of this idea requires sensing the zero-crossing of the voltage across the synchronous rectifier, and sensing the threshold- crossing of the gate-drive voltage, which is indicative of the switch turn-on (or the switch turn-off) instant. In “adaptive” gate-drive schemes, fast comparators attempt to match the zero- crossing and the threshold-crossing instants in each switching cycle, which in practice results in suboptimal performance be- cause of the comparator delays and sensitivity to parameter and temperature variations. Better results have been reported with schemes based on the “predictive” gate drive technique [1], or with delay-locked loops [3]–[5]. These techniques can reduce the dependence on very 0885-8993/$20.00 © 2006 IEEE