1 Material Characterization and Die Stress Measurement of Low Expansion PCB for Extreme Environments D. Scott Copeland a , M. Kaysar Rahim a , M. Saiful Islam a Jeffrey C. Suhling a , Richard C. Jaeger b , Pradeep Lall a and Guoyun Tian b a Department of Mechanical Engineering b Department of Electrical and Computer Engineering Auburn University Auburn, AL 36849 Phone: 281-226-4731 E-Mail: david.s.copeland@boeing.com Kris Vasoya ThermalWorks, Inc. 9042 Garfield Avenue, Suite 212 Huntington Beach, CA 92646 Phone: 714-960-5152, Ext 202 Email: Kris.Vasoya@ThermalWorks.com Abstract—This study characterizes a low expansion PCB composed of STABLCOR ® /FR4 laminate that is suitable for flip-chip applications exposed to extreme operating environments from –55°C to +150°C 1,2,3 . We demonstrate that the STABLCOR ® /FR4 laminate exhibits approximately 80% reduction in CTE and greater stiffness characteristics as compared to typical FR4 material. Additionally, we demonstrate that the laminate successfully passes flammability, thermal vacuum stability, and toxicity testing as required for pressurized and un-pressurized Space applications. Fabricated (111) silicon test chips incorporating integral piezoresistive sensors were utilized to measure the die stresses during the underfill cure process, and in the final cured assemblies. Additionally, die stress measurements were performed as a function of temperature post cure with each PCB type. During the snap cure cycle of the underfill, changes in the stresses on the die surface contacting the underfill were observed due to encapsulant shrinkage. However, it was also found that the majority of the final assembly die stresses are built up during the cooling of the flip chip assembly after cure. The STABLCOR ® /FR4 laminate was found to have significantly lower magnitude of final assembly die stresses as compared to typical FR4 materials at most sensor locations. TABLE OF CONTENTS 1. INTRODUCTION...................................................... 1 2. MATERIAL CHARACTERIZATION.......................... 2 3. PIEZORESISTIVE SENSORS .................................... 7 1 0-7803-8870-4/05/$20.00© 2005 IEEE 2 STABLCOR is a registered trademark of ThermalWorks, Inc. 3 2005 IEEE Aerospace Conference, Paper Number: 1031 4. STRESS TEST CHIPS .............................................. 9 5. TEST BOARD ASSEMBLY..................................... 10 6. FLIP CHIP STRESS MEASUREMENTS .................. 12 7. SUMMARY AND CONCLUSIONS ........................... 17 ACKNOWLEDGMENTS............................................. 18 REFERENCES........................................................... 18 BIOGRAPHY ............................................................ 19 1. INTRODUCTION Flip-Chip technology, using bare integrated circuit die mounted directly on the printed circuit board, is gaining acceptance in many commercial applications that are exposed to benign thermal environments, including digital watches, cellular phones, disk drives, and personal digital assistants. Reliability issues arise when using flip-chip packaging technology in electronic assemblies exposed to harsh operating environments such as space or automotive underhood applications. Solder interconnect failures due to thermal and vibration fatigue is one major reliability issue facing today’s electronic packaging technologies [1]. Repeated thermal cycling over large temperature ranges leads to low cycle solder joint fatigue failures due to thermally induced strains. These strains result from uneven expansions and contractions of the various materials due to mismatches in the coefficients of thermal expansion (CTE). Flip-chip packages are particularly susceptible to this failure mechanism due to the severe CTE mismatch between the silicon die and that of the typical FR4 PCB material. Knowledge of the stresses that occur at the flip chip die surface can be used to characterize underfill adhesion and reliability of the die underfill interface. The die stresses can also be used to compare the effects of various PCB coefficients of thermal expansions (CTE) on solder joint strains. In this study, we have utilized (111) silicon test