A Framework for Energy and Transient Power Reduction during Behavioral Synthesis Saraju P. Mohanty and N. Ranganathan Department of Computer Science and Engineering Nanomaterial and Nanomanufacturing Research Center University of South Florida Tampa, FL 33620 smohanty@csee.usf.edu and ranganat@csee.usf.edu Abstract In deep submicron and nanometer designs for battery driven portable applications, the minimization of total en- ergy, average power, peak power, and peak power differ- ential are equally important. In this paper, we propose a framework for simultaneous reduction of these energy and transient power components during behavioral synthesis. A new parameter called ”Cycle Power Profile Function” (CPF) is defined which captures the transient power char- acteristics as a weighted sum of mean cycle power and mean cycle differential power. Minimizing this parame- ter using multiple voltages and dynamic clocking results in reduction of both energy and transient power. Based on the above, a datapath scheduling algorithm called ”CPF- Scheduler” is developed which attempts to minimize the CPF. Experimental results show that for two voltage levels, three operating frequencies, switching activity of 0.5 and power profiling factor of 0.5, the scheduler achieves (i) to- tal energy reductions in the range of 27 − 53%, (ii) average power reductions in the range of 40 − 73% (iii) peak power reductions in the range of 58 − 78% and (iv) peak power differential reductions in the range of 60 − 97%. Further, the impact of switching, profiling factor and resource con- straints on the power profile is studied in detail. 1 Introduction The low power circuit design is a three dimensional problem involving area, performance and power trade-offs. Because of decreasing feature size and increasing packing density, it may be possible to trade area against power. With the increasing clock frequency, this trend has made relia- bility a big challenge for the designers, mainly bacause of high on-chip electric fields [16, 17]. Several factors such as, demand of portable systems, thermal considerations, envi- ronmental concerns and reliability issues have resulted in the need for low power design. In deep submicron and nanometer designs for low power, the total energy, aver- age power, peak power and peak power differential are all equally important considerations. Both peak power and peak power differential drive the transient characterstics of the CMOS circuit. The life time and efficiency of battery is affected by all of the above parameters [8], since higher the current (power) lesser the electrochemical conversion efficiency. Reduction of average current (power) is essen- tial to enhance noise margin (to decrease functional fail- ures) and to increase electromagnetic reliability. The peak power affects packaging and cooling costs, functional fail- ures, hot-electron effects (leading to runaway current fail- ure) and electrostatic discharge failure. Reduction of cur- rent (power) fluctuation is necessary to reduce power sup- ply noise (reducing di/dt), cross-talk and other electromag- netic noise. From the above discussion, it is observed that simultaneous minimization of all the four power and energy factors is important. The three sources of power dissipation in a CMOS digi- tal circuit are dynamic power (P d ), short-circuit power (P sc ) and static power (P s ) as summerized in Eqn. 2 below [10] : P total = P d + P sc + P s (1) P total = αCV 2 f clk + τ αV I sc f clk + VI leak (2) where, α is the switching activity, C is the total capacitance seen at the gate output, V is the supply voltage, f clk is the operating frequency, τ is the time for which short-circuit occurs, I sc is the short-circuit current and I leak is the leak- age current. In [17], the authors indicate that there is an in- crease in both dynamic and static power in nanometer tech- nology domain. The dynamic power component is signif- icant due to increased switching activity in large circuits. In this work, we focus on the dynamic power aspect of the datapath circuits. It is well known that [3, 10], (i) by re- ducing supply voltage both power and energy can be saved