Comparative Analysis of Double Gate FinFET Configurations for Analog Circuit Design Dhruva Ghai 1 , Saraju P. Mohanty 2 and Garima Thakral 3 . Dept. of Electronics and Communication Engineering, Oriental University, Indore, India. 1 Dept. of Computer Science and Engineering, University of North Texas, USA. 2 Dept. of Computer Science, Oriental University, Indore, India. 3 Email-ID: dhruvaghai@orientaluniversity.in 1 , saraju.mohanty@unt.edu 2 , and garimathakral@oriental.ac.in 3 . Abstract— FinFETs are being adopted as an alternative to nanoscale classical MOSFET for digital circuits. The double- gate (DG) FinFET gives rise to a rich design space using various configurations of the gates. Existing research study the DG FinFET for digital design. However, the effectiveness of the various DG FinFET configurations for the analog design has not received much attention. In this paper, we compare the DG FinFET parameters including transconductance (gm), output resistance (r0), open-circuit gain (gm × r0), transition frequency (fT ) including the most important issue, “nanoscale variability”, which are important for analog design. The following three configurations for a fully depleted SOI DG FinFET are analyzed: shorted-gate, independent-gate, and low-power, for both strong inversion and subthreshold operations. Using the results obtained, we present guidelines for DG FinFET based analog design. I. I NTRODUCTION AND CONTRIBUTIONS Nanoscale bulk CMOS technology suffers from various short channel effects (SCEs), threshold voltage fluctuations, and process variations. One of the new devices being explored is the FinFET technology, due to its higher immunity to SCEs and process variation [2], [3]. FinFETs have advantages like a higher  I ON I OFF  ratio (very important for digital circuits) and smaller intrinsic gate capacitances and design flexibility at with multiple gates. For a double-gate FinFET, three config- urations are identified: shorted-gate (SG) mode with transistor gates tied together, low-power (LP) mode where the back-gate is tied to a reverse-bias voltage to reduce leakage power, and independent gate (IG) mode where independent signals are used to drive the two device gates. The question is how good is each of the DG FinFET configurations for analog designs. The digital circuits are the main workhorse in the consumer electronics in which, devices are built for a high  I ON I OFF  ratio. The digital chips utilize FinFET devices are in production [1]. However, for analog designs, a high  I ON I OFF  ratio, may not lead to best performance. The design trade-offs for analog circuit design are more complicated than those for digital. If instead of bulk CMOS, the FinFET will be used, the device architecture will change, and more interpretation time will be required for optimal circuits to be designed. The FinFET based digital circuits are being explored [4], [5]. In [6], a FinFET-based SRAM is optimized using back- gate voltage tuning. In [7], FinFET is optimized for low- voltage analog design. In [8], the analog performance of DG and Tri-Gate FinFET are compared. In [9], the analog/RF per- formance of FinFET are compared with bulk CMOS. However, there is no comparison between the various configurations of the FinFET device for analog applications. This paper is an effort in the direction of exploring the FinFET technology for analog circuit design. The novel con- tributions of this paper can be summarized as follows: 1) A comparative analysis among the configurations of the FinFET device is presented for analog circuit design. 2) Output resistance, Transconductance, Open-circuit gain, transition frequency are analyzed in both strong inver- sion and subthreshold regions. 3) Statistical process variation analysis is presented for the above FinFET parameters in both strong inversion and subthreshold regions of DG FinFET operation. 4) Design guidelines are formed for the analog circuit designer working with FinFET configurations. II. DG FINFET: MODEL AND CONFIGURATIONS The FinFET is inherently an SOI transistor. The body thick- ness (T Si ) of a fin is analogous to silicon channel thickness. Fig. 1 shows the shorted-gate (SG), independent-gate (IG) and Low-Power (LP) structures of a n-type FinFET. V gf is the potential difference between the front gate and source. V gb denotes the potential difference between the back gate and the source. In the SG mode, the front and back gates are tied together. In the IG mode, the top part of the gate is etched out for two independent gates [7]. The LP-mode applies a reverse- bias voltage to the back-gate in order to reduce subthreshold leakage. SG mode has smallest delay, followed by IG and LP mode [2]. For power consumption, LP mode gives the lowest power consumption, followed by IG and SG mode. Digital design mainly deal with with delay and power. In the typical FinFET process, the SOI thickness (T si ) is so thin that the silicon body is fully depleted. Two single-gate transistors have been used to capture the current conduction controlled by the front and back gate in a DG FinFET transistor [3]. Each sub-transistor has its own definitions of gate voltage (V g ), threshold voltage (V Th ), and gate-oxide thickness (T ox ). The fully depleted SOI model of BSIM (BSIM FD SOI) is used for each sub-transistor. The key parameters for the FinFET model for 32nm node are shown in Table I. For brevity, results for a n-type DG FinFET device is presented while dual trends are observed for p-type.