Design of a Low Power Image Watermarking Encoder using Dual Voltage and Frequency Saraju P. Mohanty Dept. of Computer Science and Engineering University of North Texas, Denton, TX 76203 Email: smohanty@cs.unt.edu N. Ranganathan and K. Balakrishnan Dept. of Computer Science and Engineering University of South Florida, Tampa, FL 33620 Email: ranganat@csee.usf.edu Abstract In this paper, we propose a VLSI architecture and provide prototype implementation of a chip that can insert both invisible and visible watermarks in DCT domain. To our knowledge, this is the firstever low power watermarking chip having such watermarking functionalities. Various techniques, such as multiple voltages, multiple frequency, and clock gating are incorporated to reduce power con- sumption of the chip. The proposed architecture has a three stage pipeline structure and also uses parallelism to improve the overall performance. A prototype chip is designed and verified using various Cadence and Synopsys tools using TSMC technology. It runs at a dual frequency of and and at a dual voltage of and and contains transistors. The average power consumption of the chip is estimated to be , which is five times less than its single supply voltage and single frequency operation. 1 Introduction Watermarking is the process that embeds data called a watermark, tag or label into a multimedia object, such as images, video or text for their copyright protection and au- thentication. The invisible watermark is embedded in such a way that alternations made to the pixel value is percep- tually not noticed, whereas, in visible watermarking a sec- ondary translucent is overlaid into the primary image. In in- visible watermarking scheme, the watermark is detected or extracted to make an assertion about the object. The wa- termark can be applied in either spatial or frequency do- main. Frequency domain is preferred over spatial domain in the applications in which robustness is the most desired characteristics. The above JPEG codec can be a part of a scanner, a digital camera, or any other multimedia device so that the digitized images are watermarked right at the ori- gin. The hardware implementation watermarking schemes has advantages over the software implementation in terms of low power, high performance, and reliability. A comparative view of the watermarking chips available in current literature is provided in Table 1. Strycker, et. al. [3] proposed the implementation of a real-time spatial do- main watermark embedder and detector on a Trimedia TM- 1000 VLIW processor. Mathai, et. al. [4] present a chip implementation of the same video watermarking algorithm. A DCT domain invisible watermarking chip is presented by Tsai and Lu [5]. Garimella, et. al. [6] proposed a VLSI architecture for invisible-fragile watermarking in spatial do- main. Mohanty, et. al. [1] described a watermarking chip that has spatial domain invisible robust and fragile water- marking functionalities. Mohanty, et. al. [2] propose a chip that has two spatial visible watermarking functionalities. Table 1: Watermarking Chips in Current Literature Work Type Object Domain Chip Statistics Mathai, Invisible Video Wavelet et. al. [4] Robust Tsai and Invisible Image DCT , Lu [5] Robust , , Garimella Invisible Image Spatial , et. al. [6] Fragile , Mohanty Robust Image Spatial , , et. al. [1] Fragile , Mohanty Visible Image Spatial , et. al. [2] , , In this paper, we propose chip that has both invisible and visible DCT domain watermarking functionalities. The low power feature such as, multiple supply voltages, dynamic frequency clocking, and clock gating have been used to keep the power consumption of the chip at minimal. The perfor- mance improvement is done with a three stage pipeline and parallel architecture. Single supply level low power consum- ing level converters are used to interface modules operating at different supply voltages. The lower supply voltage mod- ule is run at a lower frequency. The architecture uses a de- centralized controller mechanism to facilitate the dual volt- age, dual frequency and clock gating implementations.