Impact of Gate-Oxide Tunneling on Mixed-Signal Design and Simulation of a Nano-CMOS VCO ⋆ Elias Kougianos and Saraju P. Mohanty VLSI Design and CAD Laboratory (VDCL) University of North Texas, Denton, TX 76203, USA. Abstract Design optimization for performance enhancement in analog and mixed signal circuits is an active area of research as technology scaling is moving towards the nanometer scale. This paper presents an approach towards the efficient simulation and characterization of mixed signal circuits, using a 45nm CMOS voltage controlled oscillator (VCO) with frequency divider as a case study. The performance characteristics of the analog and digital blocks in the circuit are simulated and the accuracy issues arising due to separate analog and dig- ital simulation engines are considered. The tremendous impact of gate tunneling current on device performance is quantitatively analyzed with the help of an “effective tunneling capacitance”, which allows accurate modeling and simulation of digital blocks with almost analog accuracy. To meet the design specifications of the analog VCO using digital CMOS technology, we follow a design of experiments (DOE) approach. The functional specifica- tions of the VCO optimized in this design are the center frequency and minimization of overall power consumption as well as minimization of power due to gate-oxide tunneling current leakage, a component that was not important in previous generations of CMOS technologies but is dominant at 45nm and below. Due to the large number of available design parameter (gate-oxide thickness and transistor sizes), the concurrent achievement of all optimization goals is difficult. A DOE approach is shown to be very effective and a viable alternative to standard design exploration in the nanometer regime. Key words: Nanoscale CMOS, Gate-oxide tunneling, Gate-oxide leakage, Voltage controlled oscillator, Design of experiments ⋆ Preliminary versions of this research has been presented in the following conferences: G. Sarivisetti, E. Kougianos, S. P. Mohanty, A. Palakodety, and A. K. Ale, “Optimization of a 45nm CMOS Voltage Controlled Oscillator using Design of Experiments”, in Proceed- ings of the IEEE Region 5 Technology and Science Conference, pp. 87-90, 2006. S. P. Mohanty and E. Kougianos, “Impact of Gate Leakage on Mixed Signal Design and Simulation of Nano-CMOS Circuits”, in Proc. 13th NASA Sympo. VLSI Design, 2007. Email address: eliask@unt.edu, saraju.mohanty@unt.edu (Saraju P. Mohanty). Preprint submitted to Elsevier 11 September 2008