IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 5, NO. 2, MARCH/APRIL 1999 261 The AMOEBA Switch: An Optoelectronic Switch for Multiprocessor Networking Using Dense-WDM Ashok V. Krishnamoorthy, Member, IEEE, Joseph E. Ford, Member, IEEE, Fouad E. Kiamilev, Member, IEEE, Richard G. Rozier, Member, IEEE, S. Hunsche, Keith W. Goossen, Member, IEEE, B. Tseng, James A. Walker, J. E. Cunningham, W. Y. Jan, and Martin C. Nuss, Member, IEEE Abstract— We present a single-chip asynchronous multipro- cessor optoelectronic bit-sliced arrayed (AMOEBA) crossbar switch. The AMOEBA switch addresses the challenge to produce a large-scale, nonblocking packet switch through dense integration of photonic devices directly onto silicon VLSI circuits. Optoelectronic-VLSI technology is used to integrate the switch fabric, routing controller, packet buffers, line interface circuits, and optoelectronic conversion devices on a single chip. We show how free-space optical interconnects and wavelength-and-space–division-multiplexed networking on single-mode fibers can provide switched interconnection between multiple nodes in a distributed computing environment. An optomechanical transceiver package accomplishes the free-space- to-fiber interfacing. We report the implementation and testing of the key components of a 16-channel AMOEBA prototype switch with a potential capacity of 12.8 Gb/s (or 800 Mb/s/channel), and capable of switching 16 million packets per second. Index Terms—CMOS integrated circuits, fiber networks, flip- chip devices, integrated optoelectronics, modulators, optical ar- rays, optical interconnections, quantum-well devices, switching, wavelength-division multiplexing. I. INTRODUCTION I T IS BECOMING evident that networking multiple general-purpose processors or workstations is an efficient and cost-effective path to high-performance computing. In such distributed computing environments, the interconnection network is typically the performance bottleneck, especially as electrical interconnect technologies struggle to keep pace with increasing demand for more connectivity and rapidly diminishing processor clock-cycle times. Historically, the network transmission bandwidth (in Megabits per second) has kept pace with the processor computing bandwidth (in millions of instructions per second), as shown in Fig. 1. However, as the performance of both the processors and the network interface cards scale up, the switching/routing functions required of the network will become the limiting bottleneck. The demands made on such a multiprocessor interconnection network will include: 1) high throughput communication; 2) low contention; and 3) simple communication protocols. Additional features of low latency data transport and packet switched operation (potentially with variable-length packets) Manuscript received November 16, 1998; revised April 29, 1999. A. V. Krishnamoorthy, J. E. Ford, R. G. Rozier, S. Hunsche, K. W. Goossen, B. Tseng, J. A. Walker, J. E. Cunningham, W. Y. Jan, and M. C. Nuss are with Bell Laboratories, Lucent Technologies, Holmdel, NJ 07733 USA. F. E. Kiamilev is with the University of North Carolina, Charlotte, NC 28223 USA. Publisher Item Identifier S 1077-260X(99)06053-0. Fig. 1. Evolution of workstation computing performance, measured ap- proximately in millions of instructions-per-second (MIPS), versus network bandwidth, measured in megabits-per-second of the network interface card (NIC). may be desirable. Markets for such networks at the campus- wide level (i.e., local area networks) as well as within an equipment room (system-area networks) are now emerging. A number of photonic technologies are candidates for multiprocessor switching and routing networks. Performance, scalability, and cost will be critical. We are investigating interconnection networks based on fiber and surface-normal optical interconnects for data-transport and silicon VLSI for switching. We employ an optoelectronic-VLSI (OE-VLSI) technology capable of supporting several thousand optical in- put/output (I/O) devices with each device capable of data trans- mission in excess of 1 Gb/s when driven with standard CMOS circuits. The specific OE-VLSI technology we discuss is based on the hybrid flip-chip bonding of GaAs–AlGaAs multiple- quantum-well (MQW) diodes onto CMOS chips followed by the removal of the GaAs substrate [1]. This technology permits the design of CMOS circuits with submicrometer feature-size and full circuit and layout optimization typical of complex VLSI chips [2], [3]. In this paper, we present the application of this technology to an asynchronous multiprocessor optoelectronic bit-sliced array (AMOEBA) switched network. The AMOEBA switch is intended to function as a high-performance central switch on a data network serving multiple processors or computers in tightly coupled computing environments (single frame), loosely coupled environments ( 100 m), or campus-wide net- works ( 1 km, limited by fiber attenuation at the operating 1077–260X/99$10.00  1999 IEEE