REVIEW PAPER International J. of Recent Trends in Engineering and Technology, Vol. 3, No. 4, May 2010 74 © 2010 ACEEE DOI: 01.IJRTET.03.04.176 Encoding Schemes for Reduction of Power Dissipation, Crosstalk and Delay in VLSI Interconnects: A Review S.K.Verma 1 and B.K.Kaushik 2 1 Department of Computer Science and Engineering, G.B. Pant Engineering College, Pauri-Garhwal, INDIA 2 Department of Electronics and Computer Engineering, Indian Institute of Technology-Roorkee, INDIA Email: skverma.gbpec@rediffmail.com ; brajesh_k_k@yahoo.com Abstract—This paper reviews different encoding schemes for reduction of power dissipation, crosstalk noise and delay. Crosstalk is aggravated by enhanced switching activity which is often main cause for the malfunctioning of any VLSI chip. Consequently, delay and power dissipation also increases due to enhanced crosstalk. Reduction in switching activities through coupled transmission line results in enormous reduction of power dissipation, crosstalk and delay. The researchers therefore often concentrate on encoding schemes that reduces the transitions of the signals. This paper reviews all such encoding schemes. Index Terms—VLSI, CMOS, Interconnects, Encoding, SoC. I. INTRODUCTION The factors which affect the performance of the VLSI chips are Power dissipation, Crosstalk, Delay and Noise. Dynamic power is mainly due to the charging and discharging of the capacitive load. The dynamic power dissipation is due to switching activity in a CMOS circuit. Power can be reduced by intercommunication and interconnect optimization by data encoding technique. Crosstalk effect has two categories, Crosstalk glitches and Crosstalk delays. The magnitude of glitches depends on the ratio of coupling capacitance to the line to ground capacitance. Although crosstalk delay is also created by the same coupling effect among interconnect lines but it can be produced even if line drivers are balanced. A interconnect can be modeled in two ways, RC and RLC model. There are various encoding techniques to reduce the power dissipation, crosstalk, delay and noise in interconnect.The main sources of noise are: interconnect cross capacitance noise, charge sharing noise, charge leakage noise, power supply noise, and mutual inductance noise. These noises create unwanted deviation in currents and voltages at various nodes in the VLSI circuits (Bayoumi et.al. 2005) [1]. II. ENCODING TECHNIQUES FOR REDUCTION OF POWER DISSIPATION Low Power Coding (LPC) is used for reduction of self-switching or coupling power in address bus and data bus. Encoding schemes in address bus utilize the behavior of regularity and sequentiality property. Burleson et.al. [2] proposed an encoding scheme known as Bus Invert (BI) coding. In this scheme, entire buses are used for encoding purpose and include a redundant bit along with bit line. This encoding scheme is simple and effectively minimizes the switching activities. Similar to this encoding scheme, Partial Bus Invert (PBI) is proposed by Shin et.al. [3]. In this scheme, a partial bus data are encoded in place of entire bus. Yoo and Choi[4] advanced PBI by proposing Interleaving PBI code. In this scheme the bit width and group of lines are dynamically changed. Further, PBI is again extended with Decomposed Bus Invert coding (DBI) proposed by Hong et.al. [5]. in this encoding the bus lines are grouped into any arbitrary number of groups and each group is considered separately for BI coding.The SILENT technique is proposed by Lee et.al. [6] to reduce power dissipation in the serial line. In this technique, data is encoded as XOR between the continuous data words. In the receiver side, original transmitted data word can be recovered by XOR of encoded word and previously decoded words. Transition skewing coding scheme proposed by Akl et al. [7] reduces power dissipation and area. This scheme deals with crosstalk, peak energy and current, switching and leakage power, repeaters area, signal integrity and noise. The authors used 90nm technology to simulate. This method of coding is efficient for the energy and area with low encoding and decoding latency overhead. The work has been further extended in 90-nm encoding scheme [8] considering 2-GHz global clock frequency. Kalyan et al. [9] proposed an encoding scheme to minimize on-chip interconnect energy consumption. The authors transmit the data using variable cycle transmission method based on the delay savings achieved through variable cycle transmission methods at regular intervals. Duvall, Chen and Nooshabadi [10] proposed a memory-less encoding scheme. They implemented this scheme for 8-bit bus in 65nm CMOS technology. They also present the 11-wire solution. The same circuitry of encoder and decoder has been used for the buses of 16, 32 and 64 bits and produced the same result. III. ENCODING TECHNIQUES FOR REDUCTION OF COUPLING POWER In the deep submicron technology (DSM), inter-wire capacitance and crosstalk are the major problems which cause power dissipation. The coupling capacitance not only depends on the structural and other characteristics