Adaptive GA: An Essential Ingredient in High-Level Synthesis Florence Choong Chiao Mei, Somnuk Phon-Amnuaisuk, Mohammad Yusoff Alias and Pang Wai Leong Abstract— High-level synthesis, a crucial step in VLSI and System on Chip (SoC) design, is the process of transforming an algorithmic or behavioral description into a structural specification of the architecture realizing the behavior. In the past, researchers have attempted to apply GAs to the HLS domain. This is motivated by the fact that the search space for HLS is large and GAs are known to work well on such problems. However, the process of GA is controlled by several parameters, e.g. crossover rate and mutation rate that largely determine the success and efficiency of GA in solving a specific problem. Unfortunately, these parameters interact with each other in a complicated way and determining which parameter set is best to use for a specific problem can be a complex task requiring much trial and error. This inherent drawback is overcome in this paper where it presents two adaptive GA approaches to HLS, the adaptive GA operator probability (AGAOP) and adaptive operator selection (AOS) and compares the performance to the standard GA (SGA) on eight digital logic benchmarks with varying complexity. The AGAOP and AOS are shown to be far more robust than the SGA, providing fast and reliable convergence across a broad range of parameter settings. The results show considerable promise for adaptive approaches to HLS domain and opens up a path for future work in this area. I. I NTRODUCTION T HE enormous progress in VLSI and CAD technology to support automated high-level synthesis has helped to shorten the time to market digital integrated circuits. High- level synthesis is the process of transforming a behavioral description into a structural one [1]. From the input spec- ification, the synthesis system produces a description of a data path, that is, a network of registers, functional units, multiplexers, and buses. The synthesis must also produce the specification of the control path. There are many different structures that can be used to realize a given behavior. HLS specifies the functions the chip has to perform and the way the chip interacts with its environment. This results in a so-called data-path and a controller description. The data-path consists of building blocks such as functional units, memory, and an interconnection structure among them. The controller describes how the flow of data inside the data- path is managed, and is described in terms of states and state transitions. The controller description is translated into an implementation at the abstraction level of gates by using logic synthesis. Building blocks inside a data-path are created by using so-called module generators. There are several possibilities to generate modules. The desired functionality Florence Choong Chiao Mei, Somnuk Phon-Amnuaisuk, Mohammad Yusoff Alias and Pang Wai Leong are with Multimedia University, Jln Multimedia, 63100 Cyberjaya, Selangor Darul Ehsan, Malaysia. emails: florence;somnuk.amnuaisuk;yusoff; wlpang@mmu.edu.my This material is based upon work supported by the Ministry of Science, Technology and Innovation of Malaysia (MOSTI) under Grant No. 01-02- 01-SF0068. can be described by boolean functions, and logic synthesis can be used to optimize and map the equations on a gate library, called behavioural generation. Structural generation uses knowledge of a possibly efficient structural implementa- tion, and therefore generates such a structure directly. Finally, if a layout of a module is very regular (such as RAMs, ROMs, and register files), the layout description can be generated directly. The final synthesis step, called layout synthesis, creates a geometrical description of the layout using placement and routing techniques. The result is a layout mask, which is a description of the IC at the physical abstraction level. One of the main tasks of high-level synthesis is to find the structure that best meets the constraints while minimizing other costs. For example, the goal might be to minimize area while achieving a certain required processing rate [1]. The HLS process can be divided into the three subtasks operation scheduling, resource allocation, and resource binding. The operation scheduling assigns each operation in the design to a time step in which it will be executed. Resource allocation determines the types (e.g., adder, multiplier, or register) and the number of these types of resources that should be included in the design. Resource binding determines which resources that should be used to implement each specific operation. A lot of research has been put into the area of HLS of digital systems and now HLS techniques have started to mature and find their way into commercial products. There has been during the last decade a growing interest in algorithms that are based on the principal of evolution and the survival of the fittest. A common term refers to such techniques as evolutionary computation [2]; genetic algorithms and evolutionary programming are among the best known approaches within this class. An important advantage of evolutionary computation is that they do not need special pre-knowledge about the problem space. Furthermore, they are global in scope, and can handle nonlinear, discrete, continuous or mixed search spaces, thus making them espe- cially suitable for tackling difficult and complex optimization problems. Genetic algorithms (GA’s) [3] are robust search and op- timization techniques based on the principle of Darwinian natural selection and that of Mendel’s genetic mutation. The robustness of GA’s derives from their capacity to locate the global optimum in multimodal function, which exists widely in engineering problems. Several researchers have applied GAs to the problem of simultaneously considering the subtasks of scheduling and resource allocation during high-level synthesis [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14]. However, GA often suffers from premature convergence, a phenomena that occurs when the popula- 3838 978-1-4244-1823-7/08/$25.00 c 2008 IEEE