Wideband mmWave CML Static Divider in 65nm SOI CMOS Technology Daeik D. Kim, Choongyeun Cho IBM Semiconductor R&D Center Hopewell Junction, NY Email: {dkim, cycho}@us.ibm.com Jonghae Kim Qualcomm San Diego, CA jonghaek@qualcomm.com Jean-Olivier Plouchart IBM T. J. Watson Research Yorktown Heights, NY plouchar@us.ibm.com Abstract—A wideband millimeter-wave (mmWave) CML static divider fabricated in 65nm SOI CMOS technology is presented. The mmWave system realization trend and engagement in sub- 100nm CMOS technologies are summarized. CML static divider’s circuit analysis, sensitivity curve, and simulations are explored. The input-locking hysteresis and divider DC bias tuning are employed to extend the divider operation range. The divider performance measurements are presented with hysteresis-assisted gain and figure-of-merits. A scalable statistical estimation is proposed, and it is validated with a full 300mm wafer measure- ments. The divider exhibits wideband mmWave performance to overcome the process variability in sub-100nm CMOS processes. I. I NTRODUCTION The 60GHz range milli-meter wave (mmWave) physical links are emerging as a next generation short-range wide- bandwidth communications channel [1], [2]. The CMOS tech- nology is becoming a strong candidate for the mmWave system design platform due to its manufacturing capability, system- on-chip (SoC) integration with baseband and digital intellec- tual property, and high-speed performance through technology scaling [3]. As CMOS FET’s gate length scales aggressively, the device density has increased, and high-speed performance also has been improved down to 45nm. For example, 45nm SOI NFET’s f T is beyond 400GHz [4], and it provides enough design margin for mmWave analog system, though the device speed will reach the physical limit soon [5]. The adversaries of sub-100nm CMOS are the up-front costs for development and mask [6], and the aggravated defects and process variabil- ity [7], [8]. The variability affects the analog clock generation and transceiver front-ends of mmWave SoC more than the digital block. It is because of the small device dimension and parasitic capacitance contribution, which is relative to the total parasitic allowance. Especially the mmWave tranceiver and PLL shown in Fig. 1 are susceptible to the variation. The PLL front-end components - VCO and the pre-scaling frequency divider [9] - are potential bottlenecks for SoC chip-limited yield (CLY) due to the variability. It is essential to have a wideband tunable VCO and wideband divider to overcome the variation, while the technology stabilization is enforced. This paper presents wideband CML static divider analysis, design, and measurements in 65nm SOI CMOS, as summa- rized in Fig. 1. The mmWave system implementation trend and the technology-to-circuit interaction between CMOS and mmWave analog system design are discussed as backgrounds in II. The CML static divider design process is reviewed in III. The divider small-signal analysis, sensitivity curve, models for hysteresis between input-locked and self-oscillation modes, circuit design parameters, and simulation results are explored. In IV, divider test methodology is presented. The mmWave test setup, divider measurements, performance comparison, figure- of-merits (FoMs), process variation, and scalable statistical estimation are examined. II. BACKGROUNDS The mmWave channel realization trends are reviewed from technology and application perspectives in II-A. The increas- ing overlap and collaboration between CMOS technology and mmWave analog design are discussed in II-B. A. Application The high-definition multimedia contents are overloading existing channels with data bandwidth and the cumbersome cable connections. To meet the demands, the interests on mmWave system have been elevated for last several years [1], [10]–[12]. A survey on IEEE International Solid-State Circuits Design (III) Analysis (III-A) Sensitivity curve (III-B) Hysteresis (III-B) DC bias tuning (III-D) Simulation (III-D) Test setup (IV-A) Performance (IV-B) Figure-of-merit (IV-B) Scalable measurement (IV-C) Statistical characterization (IV-C) Test (IV) Backgrounds (II) Trend (II-A) Variation (II-B) Tech.-design interaction (II-B) mmWave SoC mmWave PLL VCO LPF PFD 1 N N Fractional divider Divider RF Back-end mmWave Front-end CHP 2 PA LNA Base- band & IP PLL PLL Fig. 1. Overview of the paper. The mmWave channel SoC implementation trend and CMOS technology-to-design interaction are reviewed (II). The PLL front-end frequency divider is the main concern in the paper, and it is susceptible to the process variability in sub-100nm along the VCO. The divider design (III) and measurements (IV) are presented. 627 IEEE 2008 Custom Intergrated Circuits Conference (CICC) 978-1-4244-2018-6/08/$25.00 ©2008 IEEE 20-4-1