KLU Sparse Direct Linear Solver Implementation into NGSPICE Francesco Lannutti, Paolo Nenzi, Mauro Olivieri DIET Sapienza – University of Roma Roma, Italy Email: nicolati@fastwebnet.it, nenzi@diet.uniroma1.it, olivieri@diet.uniroma1.it Abstract—The simulation of large digital and mixed-signal integrated circuits is one of the challenges of the electronics design automation industry. In this work, a fast linear solver, KLU, is implemented into NGSPICE circuit simulator and its performances have been verified on standard netlists. Index Terms—NGSPICE; KLU; circuit simulation; transient analysis. I. INTRODUCTION The electrical-level simulation of large circuits, consisting millions of devices, is still an open issue that limits the possibility of full chip verification and one of the grand challenges in ITRS roadmap [1, 2]. The universal tool (still after 40 years from its conception) for time domain verification of ICs is SPICE (Simulation Program with Integrated Circuit Emphasis). In this context, SPICE refers to all the circuit simulators that are based on the same algorithms of the original UC Berkeley SPICE simulator. The simulation time of transient analysis in SPICE grows super-linearly with the number of equations that describe the circuit. In [3], it has been reported that the run time per transient analysis iteration scales as O(N 1.2 ) (with “N”, the number of equations), while the double precision FLOPS (Floating Point Operation per Second) of CPUs only as O(N 0.96 ) (with “N” the number of transistors in the CPU). This difference in the exponents implies that time spent for a single transient iteration will continuously increase with the technology scaling. The efforts to reduce this widening gap can be classified in two categories: specialized algorithms and parallelization. The former approach gave birth to a class of simulators often called “fast-spice”, presenting significant speedups against standard simulators for some class of circuits (e.g. RAM). The latter approach has been pursued since the early days of SPICE [4] and parallel implementations are still developed today, in particular for the newly available GPU architectures [5]. Speedups obtained by the parallelization of the transient analysis in SPICE are in the range 2x to 24x, lower than the ones of fast-spices, nevertheless the resulting simulators are not tailored to any specific circuit topology. The parallelization of SPICE is not trivial because of the structure of the SPICE algorithm for transient analysis, shown in figure 1 (after [4]). The three highlighted operations in the inner loop are the most demanding in term of computing resources: linearization of non-linear devices around the trial operating point, conductances stamping into the modified nodal analysis (MNA) matrix and linear system solution. Figure 1. The SPICE algorithm for transient analysis, adapted from [4]. The three boxes in the inner loop are the most time consuming operations The linearization of non-linear devices is the most easily parallelizable operation because it is intrinsically SIMD (Single Instruction Multiple Data). Furthermore, being the most time consuming operation, it’s the most relevant contribution to speedup. Figure 2 shows the percent of the time spent in transient simulation for the netlists in the ISCAS 85 suite [6,7]. The BSIM3load, CAPload and RESload are the functions that compute the linear conductances and load them into the system matrix for BSIM3, capacitors and resistors devices, respectively. Their execution time sums up to 54% of the analysis time. Parallel implementations of linearization phase have been done both for CPUs using OpenMP [8] and GPUs [5]. The NGSPICE circuit simulator [9] implements, as option, the parallelization of device linearization as described in [8] for BSIM3 and BSIM4 devices (data in figure 2 have been computed with this option turned off). The speedup achieved on multicore CPUs is 2. MIXED DESIGN MIXDES 2012, 19 th International Conference "Mixed Design of Integrated Circuits and Systems", May 24-26, 2012, Warsaw, Poland