On the Design of Efficient Constrained Parity-Check Codes for Optical Recording Kui Cai Data Storage Institute, National University of Singapore Singapore 117608 Email: Cai Kui@dsi.a-star.edu.sg Kees A. Schouhamer Immink Turing Machines Inc., The Netherlands. Email: immink@turing-machines.com Abstract— This paper proposes a general and systematic way to efficiently combine constrained codes with parity-check (PC) codes for optical recording. The proposed constrained PC code includes two component codes: the normal constrained (NC) code and the parity-related constrained (PRC) code. They are designed based on the same finite state machine (FSM). The code rates are only a few tenths below the theoretical maximum. The parity-check constraint is defined by the generator matrix (or generator polynomial) of a linear binary PC code, which can detect any type of dominant error events as well as error event combinations of the system. Two approaches are proposed to design the code in the non-return-to-zero-inverse (NRZI) format and the non-return-to-zero (NRZ) format, respectively. Designing the codes in NRZ format may reduce the number of parity bits required for error detection and simplify post-processing for error correction. Finally, examples of several newly designed codes and their performances are illustrated. I. I NTRODUCTION Development of ‘efficient and powerful channel codes’ is key to ensuring good reception performance under aggressive recording conditions. For optical recording, the minimum runlength constraint has been reduced from d =2 [1] used in the compact disc (CD) and digital versatile disc (DVD) to d =1 [2] in the blu-ray disc (BD) or high-definition digital versatile disc (HD-DVD). Furthermore, the combination of Reed-Solomon (RS) outer codes and parity-check (PC) inner codes in conjunction with post-processing [3], [4] shows high potential for the next (4 th ) generation optical recording systems. Cyclic redundancy check (CRC) codes are simple and efficient error detecting PC codes, and have been used in [3], [4]. In [5], specific event error control codes are proposed. When a parity-check constraint is imposed on a channel bit stream, the modulation constraints [1] should be simultane- ously satisfied. As a result, a certain code rate loss will be incurred. Therefore, the design of efficient constrained PC codes is key to the development of PC code based receivers. In one scheme proposed by [6], the parity-check information is first calculated for each channel coded data block. This information is then encoded by a standard constrained encoder and appended to the end of the corresponding channel data block. With a rate 2/3 (1,7) code, this scheme achieves 1.5 channel bits per parity bit. However, in this scheme, the chan- nel bit-stream corresponding to the parity bits is not protected by parity-checks. Therefore, errors occurring in this portion may cause further errors during the decoding of the whole data block. Thus results in error propagation. A combi-code scheme [7] achieves high efficiency similar to [6], without introducing the parity bits related error propagation. In this scheme, the constrained PC code consists of two sliding block codes, which are designed to detect the single-bit transition shift errors. Because the two constituent codes are based on the same finite state machine (FSM), no additional channel bits are needed for stitching the two codes together. By using this scheme, efficient PC codes with d =2 constraint, which achieve 2 channel bits per parity bit, have been designed. However, this scheme has several drawbacks. First, it is not general enough, since it can only correct a specific type of error event. Second, it achieves high efficiency only for d =2 codes, and efficient combi-codes with d =1 constraint are not available. In addition, the efficiency of this approach can be further improved by using the coding method proposed in [8]. In this paper, a novel code design technique is proposed that overcomes all the drawbacks of the prior art schemes. In this scheme, the parity-check constraint is defined by the generator matrix (or generator polynomial) of a linear binary PC code. This provides a systematic way for defining the error detection criteria of constrained PC codes. As a result, the codes can detect any dominant error events or error event combinations of the system. The modulation constraint can be either d =1 or d =2 for optical recording. The rates of the designed codes are only a few tenths below the theoretical maximum. Furthermore, error propagation due to parity bits is avoided, since errors are corrected equally well over the entire constrained PC codeword. In the write path of a data storage system, a precoder, i.e. a modulo-2 integration operation, converts the binary outputs of the constrained encoder into a corresponding modulated signal. The constrained encoded bits before and after the precoder are referred to as an non-return-to-zero-inverse (NRZI) sequence, and an non-return-to-zero (NRZ) sequence, respectively. Most of the prior art schemes design codes in NRZI format. In this paper, we propose two approaches to design constrained PC codes either in NRZI format or in NRZ format. Designing the codes in NRZ format is found to be more preferable for the PC code and post-processing based detection approach. Note that although this paper focuses on designing codes for optical