Statistical Framework for Technology-Model-Product Co-Design and Convergence Choongyeun Cho 1 , Daeik Kim 1 , Jonghae Kim 1 , Jean-Olivier Plouchart 2 , and Robert Trzcinski 2 1 IBM Semiconductor Research and Development Center, Hopewell Junction, NY, USA 2 IBM T. J. Watson Research Center, Yorktown Heights, NY, USA {cycho,dkim,jonghae,plouchar,rtrzcin}@us.ibm.com ABSTRACT This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical data- driven approach identifies device characteristics that are most correlated with a product performance, and estimates performance yield. A statistical method that isolates systematic process variations on die-to-die and wafer-to-wafer levels is also presented. The proposed framework enables translations of interactions among technology, product, and model, and facilitates collaborative efforts accordingly. The proposed methodology has been applied to first three development generations of 65nm technology node and microprocessor product current-controlled oscillators (ICOs) for phase-locked loops (PLLs) that were migrated from 90nm. Automated manufacturing floor in-line characterization and bench RF measurements are used for the methodology. The ICO exhibits yield improvement of RF oscillation frequency from 47% to 99% across three different 65nm SOI technology generations. Categories and Subject Descriptors B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids General Terms Measurement, Performance, Design, Economics, Verification. Keywords Technology-Model-Product Co-design, Statistical, Yield, Process Variation, Design for Yield (DFY) 1. INTRODUCTION Currently product, model, and process are developed in a parallel fashion with not much consideration of their interplay. While this divide-and-conquer approach drives development of each component separately, it has limitation in addressing a complex interaction among components. The lack of systematic perspective on the whole IC development components hinders rapid yield learning of the target process technology node [1]. It is distinguished especially in the technology node ramp. Figure 1 exemplifies a typical technology node ramp-up timeline for product, model, benchmark, and process development for a new technology node. Here, a node refers to a technology associated with a MOSFET gate feature size (e.g. a 65nm node). A generation within a node uses a different set of masks (e.g. 65nm generations 1 and 2). An iteration employs same mask set but potentially different process recipes, at a different time. The initial benchmarking structures (B0) and product-driven circuits (P0) are commonly migrated from an earlier generation or an earlier node. On a process side, preparation for a new technology node usually begins in parallel with an initial target model (T0) development. B0 benchmarking and P0 product will be designed with T0 model. As front-end-of-the-line (FEOL) processes are done and most B0 devices are characterized, the output will be interpreted for model calibration that results in T1 model. When back-end-of-the-line (BEOL) processes end, the measurements on product circuits (P0) will provide feedback to process and model. Due to the high degree of complexity of product circuits and stringent timeline, a next generation or iteration begins before the feedback from P0 measurement is reflected in process and model. As in this illustration, the next generation (Gen 2) is developed concurrently with Gen 1. Prep Mask Preparation FEOL BEOL T0 P0 Product Model Mask Process T1 Time Node 0 Node 1 Gen 1 B0 Bench- mark Migration Migration Mask delivery B0 Interpretation Measure Feedback P0 Measure (Feedback) (Inter- pretation) Model Model Gen 2 Figure 1. A new technology node development timeline for manufacturing process, benchmarking, model and product circuit design. Fig. 2 illustrates feedback mechanism of process, benchmark, model and product. Process Model Benchmark Product Co-design & Convergence (Feedback) Measurement Model Interpretation Model (Interpretation) Measurement Feedback Figure 2. Interaction between process, benchmarking, model, and product. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC’07, June 4–8, 2007, San Diego, CA, USA. Copyright 2007 ACM 978-1-59593-627-1/07/0006…$5.00. The primary feedback to process and model comes from the test data which are experimented by benchmarking structures such as device macros, physical macros, and static ring oscillators (ROs). These test structures are designed to be sensitive to a certain set of process variations so that their impacts on circuit performance are directly monitored, and accommodated in the process development and model calibration. On the other hand, a complex and customized product circuit is difficult to provide such a feedback to either process and model because of its complicated 503 29.2