Reconfigurable Wafer-Scale Circuit Board Steady State Thermal Analysis Mohammed Bougataya 1,2 , Ahmed Lakhsasi 2 , Richard Norman, Richard Prytula 3 , Yves Blaquière 4 and Yvon Savaria 5 (1)Université du Québec à Trois-Rivières, (2) Université du Québec en Outaouais, (3) Gestion TechnoCap Inc., (4)Université du Québec à Montréal, (4)École Polytechnique de Montréal, Abstract: During the development of a reconfigurable wafer-scale circuit board, the thermal design aspects have proved crucial to its reliable operation. Reducing thermally induced stress and preventing local overheating remain major concerns in maximizing the capabilities of the WaferBoard TM technology. This paper presents thermal analysis of a reliable large WaferBoard TM capable of supporting power-hungry components with various boundary conditions. Several approaches were implemented to achieve a detailed thermal analysis. Device thermo-mechanical behavior is influenced by package geometry, solder balls interconnections, and physical heat source distribution, as well as by the WaferBoard™ design itself. For this study various thermal boundary conditions are analyzed and thermal profiles along the axes and 3D thermal contours are presented. 3D finite element thermal models are used to predict local thermal peaks on the WaferBoard TM structure. In this way we explore possibilities to minimize the thermal gradient in the critical areas, especially at the solder balls level. In a second step, thermal stress analysis is conducted using the temperature loads calculated by steady state thermal analysis. Index Terms- Thermal analysis, Heat transfer, junction temperature, VLSI, Finite Element. I- INTRODUCTION WaferBoard TM is an innovative reconfigurable circuit board for fast system prototyping. This wafer-scale application programmably interconnects integrated circuits and other components at near-intra-chip density. WaferBoard TM supports high pin-count packages of several balls per square millimeter, and provides programmable power and ground as well as signal integrity for programmable chip-to-chip connections. An innovative approach for designing and implementing a high-density programmable substrate, called WaferBoard TM , is described in the paper [1]. This envisioned technology can reduce the cost and development time of complex electronic systems by using a Wafer-Scale Integrated Circuit (WaferIC TM ) implemented with classical CMOS technologies [2]. Decreasing feature sizes and increasing power and package contact densities are making thermal issues extremely important in the WaferBoard TM design. Thermal analysis is a crucial vehicle for predicting the change in the electrical characteristics or possible stress- induces failure of a WaferBoard TM system. The device requires detailed analysis and optimization of coupling to both a heat-transfer fluid pouch used to apply even pressure, and to an underside heat sink through the WaferBoard™ itself and the supporting structures; i.e. the complete thermal coupling from component to ambient. The accurate and fast evaluation of heat flow patterns becomes an essential step in the overall design verification. The first phase consisted of studying a wide variety of possible thermal scenarios of a WaferBoard TM programmable PCB to have a preliminary idea of its thermo-mechanical behavior. As processors speeds and circuit densities increase, circuit board power density increases as well and thermal management becomes an increasingly significant part of system design [3]. The final thermal constraint is the silicon junction temperature, which remains a major obstacle for high-end circuit board performance. The miniaturization, the power, packaging, and the computation and communication frequencies of the electronic components all increase the thermal peak loads, and the thermal accumulation is a major limit to circuit and system development. The dynamic behavior of the electronic components is completely different from the static mode. In addition, emerging devices such as micro-electro-mechanical systems (MEMS) require specific packaging techniques, which have to take into account the heat dissipation constraints [4-5]. In this paper, the estimation of thermal peaks and the stress induced on the WaferIC TM (The Wafer-scale circuit at the heat of the WaferBoard™ system) has become the major issue with the increase of the power density and high switching frequency. This investigation uses a thermal heat sources emplacement approach to estimate and predict working temperature of WaferBoard TM structure. In the second step, estimated temperature gradients will be used to calculate stress profiles. Based on different scenarios, the heat sources placement is introduced. Then finite element analysis is used for