A highly reliable NBTI Resilient 6T SRAM cell Jawar Singh a,⇑ , N. Vijaykrishnan b a Department of Electronics and Communication, Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, India b Department of Computer Science and Engineering, Pennsylvania State University, USA article info Article history: Received 5 July 2012 Received in revised form 15 October 2012 Accepted 6 November 2012 Available online 8 December 2012 abstract In this work, a highly reliable six-transistor (6T) Static Random Access Memory (SRAM) cell is proposed. The proposed SRAM cell is resilient to Negative Bias Temperature Instability (NBTI), since, PMOS pull-up transistors are replaced by their counterpart NMOS pull-up transistors. We compared the different parameters and performance indices (static noise margin and energy per operation) of the proposed SRAM cell with the standard 6T and loadless 4T SRAM cells. In order to achieve full logic level in the pro- posed SRAM cell, we studied the effect of PMOS as access transistors and compared with the loadless 4T SRAM cells with and without NBTI effect. It is observed that the proposed PMOS access transistors based SRAM cell yield better reliability (120% improvement in read SNM) with marginal increase in energy per operation as compared to NMOS access transistors. The leakage current of the proposed SRAM cell is 57 less than the 4T SRAM cell. The proposed SRAM cell design has positive impact of NBTI stress and yields significant improvement in the SRAM cell reliability as compared to its counterpart standard 6T SRAM cell. Ó 2012 Elsevier Ltd. All rights reserved. 1. Introduction and motivation A systematic shift in PMOS transistor parameters due to Nega- tive Bias Temperature Instability (NBTI) over the life time of a sys- tem is becoming a significant reliability concern in nanometer regime [1]. Particularly, sub-threshold devices and circuits which demand a high drive current for operation are hugely affected by threshold shifts and drive current loss due to NBTI [15]. SRAM cells are particularly more susceptible to the NBTI effect because of their symmetric topologies. In other words, one of the PMOS transistor is always under stress if the SRAM cell contents are not flipped peri- odically. As a result, it introduces an asymmetric threshold shift in both PMOS devices of a SRAM cell. The performance and reliability (or noise margins) are significantly degraded in SRAM cells due to asymmetric threshold voltage shift of PMOS devices. However, degradation in performance of a digital CMOS circuit can be off- set by over-sizing of the PMOS devices during the design phase, but it is not applicable for SRAM cells due to device density. The area, power and performance trade-offs due to NBTI induced side effects in digital CMOS circuits have been widely explored in [8,9,20]. The reliability which can be measured in terms of Static Noise Margin (SNM) and the leakage current of standard 6T SRAM cell become more pronounced as technology scales down, since, gate leakage is exponentially dependent on the gate oxide thickness. Fig. 1 shows the comparison of normalized read Static Noise Mar- gin (SNM) and leakage current of a 6T SRAM cell for different tech- nology nodes. The minimum feature sized devices with cell ratio (CR = 2), is used for simulation using Predictive Technology Models (PTMs) [13]. It can be seen from Fig. 1 that the read SNM or in other words reliability of a 6T SRAM cell is gradually decreasing with technology scaling, while the leakage current is exponentially increasing. Moving from 130 nm to 32 nm technology node, there is a 55% reduction in the read SNM while there is a 86% increase in leakage current. Therefore, several SRAM bitcell topologies have been proposed in the recent past to address these issues [19,3,16]. NBTI weakens the pull-up (PMOS) transistors in SRAM cell, which skews the transfer characteristics of an inverter in a SRAM cell as a result degraded hold and read Static Noise Margin (SNM). Write Noise Margin (WNM) of a standard 6T SRAM may im- prove or degraded depending upon the probability of stress [11]. By weakening of pull-up (PMOS) transistors due to NBTI may im- prove WNM allowing ‘0’ to be written more easily, on the other hand a small noise may flip the ‘1’ –‘0’ quickly. In this work, we have proposed a NBTI resilient highly reliable 6T SRAM cell. The key feature of the proposed 6T SRAM design is the use of NMOS transistors only (hereafter it will be referred as 6T NMOS SRAM cell). In the proposed 6T NMOS SRAM cell, NBTI in- duced side effects are eliminated because pull-up PMOS transistors are replaced by their counterpart NMOS pull-up transistors. How- ever, the design is mostly inspired from the loadless 4T SRAM cell which is having severe leakage current problem [12]. In the pro- posed 6T NMOS SRAM cell bringing the internal data storage nodes (Q or QB) to a level V DD is difficult due to V TH drop across the NMOS access transistors. Therefore, a variant of the proposed design in 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.11.003 ⇑ Corresponding author. E-mail address: jawar@iiitdmj.ac.in (J. Singh). Microelectronics Reliability 53 (2013) 565–572 Contents lists available at SciVerse ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel