Short Communication A capacitance–voltage model for polysilicon-gated MOS devices including substrate quantization effects based on modification of the total semiconductor charge q Eric M. Vogel * , Curt A. Richter, Brian G. Rennex National Institute of Standards and Technology, Semiconductor Electronics Division, 100 Bureau Drive, MS 8123, Building 225, Room B. 370, Gaithersburg, MD 20899, USA Received 17 December 2001; received in revised form 27 January 2003; accepted 10 March 2003 Abstract We present a model for simulating the capacitance–voltage (C–V ) characteristics of polysilicon-gated MOS devices with thin oxides. The model includes substrate quantization effects through a modification of the total semiconductor charge. Therefore, solutions for C–V can be quickly obtained without the computational burden of solving over a physical grid. The model includes polysilicon depletion by self-consistently solving the charge balance equation. We conclude with comparisons of the C–V characteristics obtained with this model and those obtained by self-consistent solutionstotheSchr€ odingerandPoissonequations.Goodagreementwasobservedoverawiderangeofoxidethickness (2.0–15.0 nm) and substrate doping (10 15 –10 18 cm 3 ). Published by Elsevier Science Ltd. Keywords: MOS structure; Quantum mechanical effects; MOS model; Capacitance–voltage; Poly-depletion; Thin oxides 1. Introduction In an metal–oxide–semiconductor (MOS) device, the surface electric field in the silicon perpendicular to the Si–SiO 2 interface results in the formation of a potential well such that the motion of the free carriers normal to the interface is quantized. The quantization results in a splitting of the once continuous energy bands into dis- crete subbands such that the first energy level does not coincide with the bottom of the conduction band, and a shifting of the charge centroid away from the Si–SiO 2 interface. These quantum mechanical (QM) effects result in significant changes in device behavior as compared to the classical case, including: increased threshold voltage; reduction of the total capacitance in accumulation and inversion; reduction of drive current; and reduction in transconductance. Large transverse electric fields also result in a significant capacitance associated with the polysilicon gate. The polysilicon capacitance is domi- nant when the gate is depleted, but is also significantly present in accumulation. There have been several methods used to model or simulate the capacitance–voltage (C–V ) characteristics of MOS capacitors with thin gate dielectrics. The two primary distinctions are: (1) simulations based on self- consistent solutions to the Schr€ odinger and Poisson equations [1–10], and (2) analytical transformation or correction of classical solutions to account for the QM q Contribution of the National Institute of Standards and Technology is not subject to US copyright. Certain commer- cial equipment, instruments, or materials are identified in this paperinordertospecifytheexperimentalprocedureadequately. Such identification is not intended to imply recommendation or endorsement by the National Institute of Standards and Technology, nor is it intended to imply that the materials or equipment identified are necessarily the best available for the purpose. * Corresponding author. Tel.: +1-301-975-4723; fax: +1-301- 948-4081. E-mail address: eric.vogel@nist.gov (E.M. Vogel). 0038-1101/03/$ - see front matter Published by Elsevier Science Ltd. doi:10.1016/S0038-1101(03)00099-6 Solid-State Electronics 47 (2003) 1589–1596 www.elsevier.com/locate/sse