Electrically Driven Optical Proximity Correction Shayak Banerjee*, Praveen Elakkumanan 1 , Lars W. Liebmann 1 , James A. Culp 1 , Michael Orshansky* 1 IBM Corp., East Fishkill, NY * University of Texas at Austin, TX 78712 ABSTRACT Existing optical proximity correction tools aim at minimizing edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-k1 lithography, especially at 45nm and beyond, printing perfect polygons is practically impossible to achieve in addition to incurring prohibitively high mask complexity and cost. Given the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal and the printed contours is a more reasonable strategy. In fact, we show that contours with non-minimal EPE may result in closer match to the desired electrical performance. Towards achieving this objective, we developed a new electrically driven OPC (ED-OPC) algorithm. The tool combines lithography simulation with an accurate contour-based model of shape electrical behavior to predict the on/off current through a transistor gate. The algorithm then guides edge movements to minimize the error in current, rather than in edge placement, between current values for printed and target shapes. The results on industrial 45nm SOI layouts using high-NA immersion lithography models show up to a 5% improvement in accuracy of timing over conventional OPC, while at the same time showing up to 50% reduction in mask complexity for gate regions. The results confirm that better timing accuracy can be achieved despite larger edge placement error. Keywords: OPC, Design for Manufacturability, Design-Intent, Contour-based Current. 1. INTRODUCTION Semiconductor scaling has primarily been driven by advances in lithographic technologies allowing the printing of increasingly smaller feature sizes. Economic reasons coupled with lack of suitable resist and lens materials have, thus far, prevented migration to predicted future lithographic technologies such as 154nm or EUV lithography. Consequently, Resolution Enhancement Techniques (RET) such as sub-resolution assist features (SRAF), phase-shift masking (PSM) and optical proximity correction (OPC) have become vital to ensuring high lithographic yield at the current 193nm lithography node. Optical proximity correction (OPC) is the technique of distorting mask features to ensure that layout features print according to specifications 7 . The OPC flow consists of contour generation followed by optimization to reduce EPE (Fig. 1) between the resist contour and target feature. While this approach deals effectively with most catastrophic failures, it cannot guarantee good matching of electrical properties, placing limitations on parametric yield. Recent experiments have demonstrated that minimizing edge placement error does not necessarily guarantee desired electrical behavior of a particular feature. The essential reason is that in 45nm processes, even the most extensive conventional OPC that minimizes EPEs cannot produce intended rectangular shapes. This is due to several factors including the approaching limits of diffraction, mask errors, and variations in process conditions, which make the perfect polygonal shapes unachievable. The geometric mismatch leads to the inability to guarantee ideal electrical behavior, which affects timing accuracy and yield since transistor properties no longer match those assumed at the design stage. Additionally, at the 45nm technology node, using OPC to print perfect polygons leads to highly complex masks which suffer from high cost and mask errors 1 . In this paper we propose to modify the objective of OPC to minimize the electrical error, rather than edge placement error. Because EPE minimization no longer ensures electrical matching, we propose to use electrical matching directly as a guide to edge movement. To our knowledge, this is the first work that uses electrical matching as an explicit objective for OPC. Earlier, K. Koike et. al. 1 discussed choosing from one of several available OPC recipes on the basis of matching transistor currents at the polysilicon level. While this approach does not change the existing OPC algorithm, experiments are a pointer to the possibilities of tuning the OPC engine to meet design requirements. P. Gupta et. al. 2 explored the possibility of passing timing information of cells to the OPC engine by establishing a relationship between Design for Manufacturability through Design-Process Integration II, edited by Vivek K. Singh, Michael L. Rieger, Proc. of SPIE Vol. 6925, 69251W, (2008) · 0277-786X/08/$18 · doi: 10.1117/12.790786 Proc. of SPIE Vol. 6925 69251W-1 2008 SPIE Digital Library -- Subscriber Archive Copy