SiC Power JFET Electrothermal Macromodel Francesc Masana, Javier Chavarría, Domingo Biel, Alberto Poveda, Francesc Guinjoan, Eduard Alarcón Department of Electronic Engineering (DEE) Polytechnic University of Catalunya (UPC) Barcelona, Spain francesc.masana@upc.edu Abstract—This paper presents a SiC JFET model comprising static, dynamic and thermal features built from SPICE Analog Behavioral Modeling (ABM) controlled sources. The model is parameterized in such a way that data sheet information is enough to set it to work. The model complexity is not very high and allows for reasonably long simulation times to cope with the rather slow self heating process and still maintain enough accuracy for practical purposes. Index Terms—SiC JFET, ABM, self heating, carrier mobility, voltage controlled capacitance, RC thermal model. I. INTRODUCTION SiC has become a base material for power devices on its own. Due to its intrinsic characteristics as wider band gap, higher critical breakdown field strength and higher thermal conductivity compared to Si and despite its poorer material quality and higher price, SiC is finding its way in power applications [1,2]. Although at the beginning only two terminal devices, mainly Schotky diodes were commercially available, many three terminal devices, i.e., normally-on and normally- off JFET, MOSFET and Thyristor [3-5] are now hitting the marketplace. Of these devices, the JFET is probably the most advantageous in the overall. Technologically simpler and more reliable due to the absence of any gate oxide is also fast switching. Its main drawback is to be a normally-on device so the control policy is more involved due to safety reasons, and although it can be made normally-off, some of its advantages are lost in the way. A compromise solution is the cascode connection of a high voltage SiC JFET and a low voltage low on-resistance Si MOSFET. Whatever the approach taken, no doubt it is the SiC tree terminal device of the present days. For that reason, the need of suitable models for circuit and system design becomes a must for such devices. Ideally, these models should include both static and dynamic features and also, due to its high temperature operation capability, thermal modeling. Fortunately, the fact of being a majority carrier device simplifies the dynamic model substantially. Apart from standard SPICE models, two main approaches are available that include self heating, i.e., Analog Hardware Description Language (AHDL) [6] and SPICE Analog Behavioral Modeling (ABM) [7, 8]. Although AHDL solution can generally be faster, as the model code is compiled and linked to the simulator, its portability between different simulators is low and user has no direct access to model equations and parameters. On the other side, SPICE ABM model is interpreted by the simulator so it executes slower than AHDL but it has total portability (except for a few syntactic differences) between SPICE simulators that support ABM, while model structure, equations (if any) and parameters are readily available to the user. In the following paragraphs, we will build the model as three independent blocks for static, dynamic and thermal response that will finally be joined together into a single electrothermal model. II. STATIC MODEL The proposed model uses the standard Shockley equations to describe the current transport in the channel region.                 − +         − + − = 2 3 2 3 3 2 3 2 P GS BI P GS BI DS P DS CH P D V V V V V V V V V R V I (1)                 − +         − − = 2 3 2 3 1 3 P GS BI P GS BI CH P D V V V V V V R V I (2) Where V DS and V GS stand for drain-source and gate-source voltage, R CH is the channel resistance, V BI is the gate-channel junction built-in voltage and V P is the channel pinch-off voltage. Equation (1) is valid for the linear region while equation (2) is for the saturation region. The border condition is: ( ) GS BI P DS V V V V − − < (3) The threshold voltage, i.e., the gate-source voltage that makes the drain current zero is: P BI TH V V V − = (4) Because power JFET’s are vertical devices, drain drift region resistance is a significant part of the structure. However, temperature variation of drain resistance is probably the most important factor in the electrothermal model and it has to be considered accordingly. Temperature dependence is introduced only through the mobility so it affects channel and drift resistance. Because both This work has been supported by the grant RUE CSD2009-00046, Consolider-Ingenio 2010 Programme, Spanish Ministry of Science and Innovation.