Memristive circuits for LDPC decoding Jussi H. Poikonen 1,2 , Eero Lehtonen 2 , Mika Laiho 2 , Jonne K. Poikonen 2 1 Department of Communications and Networking (Comnet), Aalto University, Espoo, Finland 2 Technology Research Center (TRC), University of Turku, Turku, Finland Abstract—We present design principles for implementing de- coders for low-density parity check codes in CMOL-type memris- tive circuits. The programmable nonvolatile connectivity enabled by the nanowire arrays in such circuits is used to map the parity check matrix of an LDPC code in the decoder, while decoding operations are realized by a cellular CMOS circuit structure. We perform detailed performance analysis and circuit simulations of example decoders, and estimate how CMOL and memristor characteristics such as the memristor OFF/ON resistance ratio, nanowire resistance, and the total capacitance of the nanowire array affect decoder specification and performance. We also analyze how variation in circuit characteristics and persistent device defects affect the decoders. I. I NTRODUCTION In this work, we consider the use of an emerging technology — CMOL-type memristive circuits — in decoding error cor- recting LDPC codes. This is a computational task of practical significance especially in digital communication and data storage systems. We begin by briefly outlining the considered technologies and their currently perceived significance, the motivation for the considered area of computing, and the specific objectives of this work. A memristor — short for memory resistor — is a two- terminal resistive component, whose resistance changes as a function of the voltage across or the current through it. Theoretical concepts regarding memristors, which were pos- tulated by Leon Chua in 1971 [1], can be used to explain the dynamical properties of various emerging memory devices based on resistive switching, such as resistive RAM and phase-change memories [2]; in this work we assume the term memristor refers to all such devices. Various different physical realizations of memristors have been reported, for example in [3]–[6]. A natural circuit topology for the use of memristors is a nanowire crossbar structure, where a memristive device is located at each crossing of two wires. This topology allows the realization of extremely dense non-volatile random-access memories, as each memory cell consists of a single memristor, whose feature size can already be scaled down to a few tens of nanometers [3]. Memristive memory technology has been reported to be approaching commercial viability as a replacement for Flash and DRAM memories [7], [8]. The CMOL (CMOS/molecular hybrid) [9] architecture fa- cilitates the realization of a programmable communication network on top of CMOS integrated circuits by interfacing active CMOS components with passive memristive crossbars. Copyright (c) 2014 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending an email to pubs-permissions@ieee.org. Besides memory circuits, existing proposals for practical ap- plications of CMOL circuits have focused especially on imple- mentations of neuromorphic systems consisting of memdevice- based synapses and CMOS-based artificial neurons [10]–[12]. Memristive devices and systems can also be used to implement Boolean logic directly within memory arrays, as considered recently for example in [13]–[16]. CMOL-type realization of parallelized memristor logic is considered in [17]. In this work we utilize a specific benefit of the CMOL architecture: it allows programmable, nonvolatile, and area efficient connectivity between CMOS processing elements. A general drawback in the CMOL architecture is that addressing several memristors simultaneously in the associated nanowire crossbar is limited. However, we show that in the presented LDPC decoding approach this is not a significant limitation, as the considered decoding circuits consist of independent parallel processing cells, and require mainly global signaling. LDPC decoding is one of the key enablers of near-capacity information transfer in modern digital communication systems and memory circuits. Practical application of these codes is facilitated by iterative decoding, which in essence allows a shift from a complex global decoding problem to operating a large number of relatively simple parallel processing elements with complex interconnections. In general, added intercon- nection complexity in LDPC coding improves code perfor- mance, but presents significant implementation challenges in energy-efficient decoder hardware realizations. In this work we demonstrate how the CMOL architecture can be used to implement reconfigurable iterative decoding with simple CMOS designs, yielding low power and energy consumption using a 130 nm CMOS technology. Compared to conventional purely CMOS-based LDPC de- coders, the considered designs benefit from removal of the physical routing between parallel processing elements, and related routing memory and programming, from the CMOS layer. Another benefit of this approach is that performing signal processing related to error correction coding directly within, for example, CMOL-type resistive memory circuits should be more efficient in terms of design, circuit area, and energy efficiency than passing all stored data to corresponding external processing circuits. It should be noted that CMOL circuits are not yet a mature technology, which means that comprehensive measurements on their characteristics and performance are not currently available. In the following we apply published empirical data on memristive device characteristics when available, and consider analytically the effects of currently not well known circuit characteristics. Specifically, we assume memristor char-