0-7803-8906-9/05/$20.00 ©2005 IEEE 2005 Electronic Components and Technology Conference Design and Verification of Multi-Gigabit Transmission Channels Using Equalization Techniques Erdem Matoglu, Moises Cases, Daniel N. de Araujo, Nam Pham, * Phillip W Metty, ** Kent Dramstad IBM Corporation -11400 Burnet Rd. Austin, TX - * 2070 RT 52 Hopewell Jct, NY- ** 1000 River St. Essex Junction, VT Phone: 512-823-6152, email: (matoglu, cases, dearaujo, npham, mettyp, dramstad)@us.ibm.com Abstract In this paper 6.25Gbps and 5Gbps digital data transmission over copper cables up to 15m is investigated on a high-speed test board. Transmitter and receiver equalization techniques to compensate the non-ideal channel characteristic are evaluated. Signal integrity design and measurement implications of receiver side equalization are discussed. Introduction The multi-gigabit serial data transmission trend in the computing systems results in new design challenges. For example, Serial Attached SCSI (SAS) is targeting 6Gbps in 2007. The PCI Express increases from 2.5Gbps to 5Gbps in 2006 [1]. High-speed serial protocols such as SONET, Infiniband, and Fiber Channel are employed in the communication industry for many years. However, the migration of these protocols into the computing environment requires a new signal integrity design and testing approach. In order to keep the cost of computing equipment down, low cost printed circuit board (PCB) and copper interconnects will be the dominant choice of material for the backplanes and scalability cables. However, due to the limited bandwidth of these materials, high data rates on printed circuit boards and cables impose significant signal integrity challenges. This paper presents 6.25Gbps and 5Gbps digital data transmission performance on high-speed copper cables up to 15m. Several driver and receiver side channel compensation techniques are briefly summarized. Limitations of traditional design, modeling, and measurement techniques at high data rates and long cables are discussed. Digital Communication in Non-ideal Channels The basic elements of digital communication path can be categorized as the transmitter (TX), the channel, and the receiver (RX). Non-ideal performance of these elements may cause error in the data recovery. The non-ideal electrical performance can be grouped as: channel loss, deterministic jitter (DJ), and random jitter (RJ). Channel loss can be divided into conductor loss and dielectric loss. At high frequencies, conductor loss is due to the skin effect and it is proportional to the square root of the frequency. Dielectric loss is proportional to the frequency. Random jitter is a result of thermal vibrations, semiconductor doping and process variations. Deterministic jitter is caused mainly by crosstalk, simultaneous switching noise, insufficient power delivery, electromagnetic interference (EMI), duty cycle distortion, inter-symbol interference (ISI), and the discontinuities in the high-speed transmission path. Connectors and DC block capacitors are generally the discontinuities in the high-speed path. However, rather than the connectors or the capacitors, via and pad structures to mount these components create the impedance disruption [2,3]. The non-ideal effects described above results in a band- limited transmission path with frequency dependent attenuation and phase delay. Figure 1 illustrates the effect of band-limited channel on a digital pulse [4]. Figure 1 Band limited channel and the ISI effect In Figure 1, band-limited channel attenuates high frequency harmonics. Hence, in time domain the received waveform is not a perfect digital pulse, and has a pulse width wider than the bit time due to dispersion and loss. Consecutive sampling points are indicated at the received signal. For a sequence of transmitted bits, the non-zero samples at instances –T, T, and 2T add up causing the ISI. To remove or alleviate the ISI, various driver and receiver based channel compensation methods are used. These techniques are summarized in the subsequent sections. High-Speed Channel Equalization The high-speed serial chip and the test board used throughout this paper were designed by IBM Microelectronics [5]. The high-speed core is packaged in Ceramic Ball Grid Array (CBGA), and soldered to the high-speed test board. The board is connected to a PC via the parallel port and controlled through a Windows Graphical User Interface (GUI). Figure 2 shows the test board and the cable fixtures. Figure 2. High-speed test setup, cable, and fixtures 1531