RADIOENGINEERING, VOL. 16, NO. 3, SEPTEMBER 2007 113 Efficient Architecture and Implementation of Vector Median Filter in Co-Design Context Anis BOUDABOUS 1 , Lazhar KHRIJI 2 , A. BEN ATITALLAH 1,3 , P. KADIONIK 3 , Nouri MASMOUDI 1 1 Laboratory of Electronics and Information Technology (LETI), BP W 3038 Sfax - Tunisia 2 Dept. of Electrical and Computer Engineering, Sultan Qaboos University, Muscat, Oman 3 IMS Laboratory –ENSEIRB - University Bordeaux I - CNRS UMR 5818, France anis.boudabous@enis.rnu.tn; lazhar@squ.edu.om; benatita@enseirb.fr; kadionik@enseirb.fr; nouri.masmoudi@enis.rnu.tn Abstract. This work presents an efficient fast parallel architecture of the Vector Median Filter (VMF) using combined hardware/software (HW/SW) implementation. The hardware part of the system is implemented using VHDL language, whereas the software part is developed using C/C++ language. The software part of the embedded system uses the NIOS-II softcore processor and the operating system used is μClinux. The comparison between the software and HW/SW solu- tions shows that adding a hardware part in the design attempts to speed up the filtering process compared to the software solution. This efficient embedded system imple- mentation can perform well in several image processing applications. Keywords Color image, FPGA, SoPC, NIOS-II, VMF. 1. Introduction Recently, color image processing has been the subject of extensive research. Filtering is one of the most important elements of color image processing system. Its most im- portant applications are noise removal, image enhance- ment, and image restoration [2],[8],[19],[20]. A number of sophisticated multichannel filters have been developed to date for image filtering such as order statistics filters [16], polynomial filters and morphological filters [9]. Nonlinear filters applied to images are required to suppress noise while preserving the integrity of edges and detail informa- tion. To this end, vector processing of multichannel im- ages, which takes the advantage of color inter-channel dependence and avoids unpleasant drawbacks (pixel value rearranging and chromatic shift), is more appropriate com- pared to traditional approaches that use component-wise operators, instead [3], [8]. Among them, we cite the vector median filter (VMF) [3], which minimizes the distance in the vector space between the image vectors as an appro priate error criterion. It inherently utilizes the inner corre- lation between the channels and keeps the desirable properties of the scalar median; namely, the zero impulse response, and the preservation of signal edges. VMFs are derived as the maximum likelihood estimators for an expo- nential distribution when the filter output is restricted to be one of the input samples. They perform accurately when the noise follows a long-tailed distribution (e.g. exponen- tial or impulsive); moreover, outliers in the image data are easily detected and eliminated by VMF's. The main contribution of this paper is the implemen- tation of the VMF using embedded system in order to ac- celerate the execution time of the software solution. In- deed, hardware implementation (HW) is generally better than software implementation (SW) in processing speed and power consumption. First of all the VMF algorithm is coded in ANSI C language. This SW solution was rebuilt and tested using the NIOS-II processor. The execution times have been measured using timer that provides the number of CPU clock cycles. Afterwards, the HW imple- mentation of the SW critical part was done in VHDL (VHSIC Hardware Description Language) language. The main idea of our filter implementation is to exploit the advantages of the parallel structures which can be effi- ciently implemented in hardware. The interest of parallel architecture is to reduce the number of operations and to reach fast execution. For experimental test and verification, we used the STRATIX Development Board which contains EP1S40F780C5 FPGA device (Field Programmable Gate Array). The reading/writing pixels from images was run- ning on NIOS-II softcore processor embedded in FPGA and using μClinux as operating system. This partitioning has been chosen in order to achieve good timing results. This paper is structured as follows: section 2 presents an overview of VMF filter. In addition to the description of the HW/SW co-design platform, the parallel structure of the FPGA implementation is discussed in section 3. Section 4 presents the performance evaluations of SW and HW/SW solutions and, also, a comparison between both implementations is reported. Finally, conclusions are drawn in section 5.