1788 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 10, OCTOBER 2008 General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing Foad Dabiri, Student Member, IEEE, Ani Nahapetian, Member, IEEE, Tammara Massey, Member, IEEE, Miodrag Potkonjak, Member, IEEE, and Majid Sarrafzadeh, Fellow, IEEE Abstract—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft-error rates caused by single-event upsets (SEUs) is becoming exponentially greater. As a consequence of technology feature size reduction, the SEU rate for typical microprocessor logic at sea level will go from one in hundred years to one every minute. Unfortunately, the gate sizing requirements of power reduction and resiliency against SEU can be contradictory. 1) We consider the effects of gate sizing on SEU and incorporate the relation- ship between power reduction and SEU resiliency to develop a new method for power optimization under SEU constraints. 2) Although a nonlinear programming approach is a more ob- vious solution, we propose a convex programming formulation that can be solved efficiently. 3) Many of the optimal existing techniques for gate sizing deal with an exponential number of paths in the circuit. We prove that it is sufficient to consider a linear number of constraints. 4) We generalize our methodology to include nonlinear delay models and leakage power as well. As an important preprocessing step, we apply statistical modeling and validation techniques to quantify the impact of fault masking on the SEU rate. Furthermore, we adapt our method to incorporate process variation and evaluate our gate sizing technique under uncertainty. We evaluate the effectiveness of our methodology on ISCAS benchmarks and show that error rates can be reduced by a factor of 100%–200% while, on average, the power reduction is simultaneously decreased by less than 6%–10%, respectively, com- pared to the optimal power saving with no error rate constraints. Index Terms—Gate sizing, logic synthesis, optimization, power, soft error (SE). I. I NTRODUCTION S INGLE-EVENT upsets (SEUs) from transient faults have emerged as a key challenge in logic circuitry design [26]. Recent studies indicate that from 1992 to 2011, the SEU rate for logic will increase by more than a billion times and will surpass the soft error rates (SERs) of unprotected memory. As a consequence of technology feature size reduction, the SEU rate for typical microprocessor logic at sea level will go from one Manuscript received October 14, 2007; revised February 27, 2008. Current version published September 19, 2008. This paper was recommended by Associate Editor S. Vrudhula. The authors are with the Computer Science Department, University of California at Los Angeles, Los Angeles, CA 90095 USA (e-mail: dabiri@cs. ucla.edu; ani@cs.ucla.edu; tmassey@cs.ucla.edu; miodrag@cs.ucla.edu; majid@cs.ucla.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCAD.2008.2003268 in hundred years to one every minute [26], resulting in a clear need for addressing the problem in systematic way. SEU faults arise from energetic particles such as neutrons from cosmic rays and alpha particles from packaging material, generating electron–hole pairs as they pass through a semiconductor device [32]. During the ICs’ normal operation, these faults can be caused by electromagnetic interference. Transistor source and diffusion nodes can collect these charges, and a sufficient amount of accumulated charge may invert the state of a logic device, such as an SRAM cell, a latch, or a gate, thereby introducing a logical fault into the circuit’s operation. Because this type of fault does not reflect a permanent failure of the device, it is termed soft error (SE) or transient fault (TF). Advances in microelectronic technology, which shrink IC size to the nanometer range while also reducing the power sup- ply, are making electronic circuits increasingly susceptible to TFs. In fact, the reduction of the charge stored on circuit nodes, along with the decrease in noise margins, greatly increases the probability of voltage glitches temporarily altering nodes’ voltage values [4]. Meanwhile, the continuous increase in ICs’ operating frequencies makes the sampling of such glitches increasingly probable. Consequently, TFs will become a fre- quent cause of failure in many applications as the technology advances. Power consumption has been recognized as the critical constraint in modern microprocessor and application-specific designs [5], [17]. In addition, gate sizing has been one of the most effective methods for power minimization in CMOS digi- tal circuits. Unfortunately, gate sizing requirements for power reduction and resiliency against SEU are contradictory. The possible tradeoffs between gate sizing and power consumption have been studied in [7]. We consider the effects of gate sizing on SEU and incorporate the relationship between power reduc- tion and SEU resiliency, and we have developed a new method of power optimization under SEU constraints, which leverages convex programming to obtain provably optimal solutions. As an important preprocessing step and consideration, we apply statistical modeling and validation techniques. Gate sizing is a timing optimization process in high- performance very large scale integration (VLSI) circuit design. In this design process, the size of each gate in a combinational circuit is properly tuned so that circuit area and/or overall power dissipation is minimized under specified timing constraints. Gate sizing or the similar problem of transistor sizing has been an active research topic in recent years. Many approaches have been proposed before [2], [18], [21], [24], [25], [30]. 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