FPGA ARCHITECTURE OF GENERALIZED LAGUERRE-VOLTERRA MIMO MODEL FOR NEURAL POPULATION ACTIVITIES Will X. Y. Li #1 , Rosa H. M. Chan †3 , Wei Zhang #1 , C. W. Yu #2 , Ray C. C. Cheung #2 , Dong Song †3 , Theodore W. Berger †4 # Department of Electronic Engineering, City University of Hong Kong, Hong Kong 1 {xiangyuli4,wezhang6}@student.cityu.edu.hk 2 {r.cheung,chiwaiyu}@cityu.edu.hk † Department of Biomedical Engineering, University of Southern California, Los Angeles, USA 3 {homchan,dsong}@usc.edu 4 berger@bmsr.usc.edu ABSTRACT We present a full-parallelized and pipelined architecture for a generalized Laguerre-Volterra MIMO system to iden- tify the time-varying neural dynamics underlying spike ac- tivities. The proposed architecture consists of a first stage containing a vector convolution and MAC (Multiply and Ac- cumulation) component; a second stage containing a pre- threshold potential updating unit with an error approxima- tion function component; and a third stage consisting of a gradient calculation unit. A flexible and efficient architec- ture that can accommodate different design speed require- ments is generated. The design runs on a Xilinx Virtex-6 FPGA and the processing core produces data samples at a speed of 1.33 × 10 6 data frames/sec, which is 3.1 × 10 3 times faster than the corresponding C model running on an Intel i7-860 Quad Core Processor. 1. INTRODUCTION Brain represents information and controls actions through the ensemble spiking activity of subpopulations of its neu- rons [1]. Underlying spike transformations across brain re- gions, biological processes including synaptic transmissions, dendritic integrations, and spike generations, are difficult to study in vivo because these processes are highly nonlinear, dynamical and often time-varying [2]. For example, certain forms of plasticity, such as long-term potentiation (LTP) [3] and long-term depression (LTD) [4], occur in response to specific input patterns. Such plasticity, which can be viewed as a system time-varying property, is manifested as a change in input-output function. Quantitative studies of how such functions of information transmission across brain regions evolve during behavior are required in order to better under- stand the mechanism of the brain. While functional magnetic resonance imaging (fMRI) and other non-invasive imaging methods hold promise to un- derstand a cognition process [5], neither the spatial-temporal resolution, nor generalizability of these technologies are yet at a level to provide the bridge required. For instance, fMRI is insufficient for the study of the development of perception which is action-dependent [6]. Meanwhile, the spatial reso- lution of electroencephalography (EEG) is low as the signals recorded are temporal integrated from large numbers of syn- chronously active neurons in a brain region [1]. Therefore, we utilize single unit recordings from the implanted elec- trodes to identify the time and the locations of the episodes of changes in neuronal population nonlinear dynamics. Adaptive filters based on the point process framework were applied to the nonlinear dynamical model developed to track time-varying systems [7]. Previous research mod- els use continuous inputs and outputs: in encoding studies, output neuron firing rates are used instead of spikes; in de- coding studies, input neuron firing rates are used instead of spikes. Temporal resolution is lost using neuron firing rates instead of spikes. Instead, our method utilizes adaptive fil- ter based on the point-process framework [8] and we have developed a computational tool to understand the underly- ing time-varying nonlinear neural system using both natural spike inputs and outputs [7]. However, in real experimental applications, parallel computing facilities are required to an- alyze the data from large number of actual neuronal units in- volved and long duration of experiments. An efficient hard- ware model that can implement the method and reduce the computation time will be very useful for intensive biological data analysis. The major contribution of this paper consists of three parts: 1) We have developed a novel hardware model based on the Field-programmable Gate Array (FPGA) to prototype the proposed Generalized Laguerre-Volterra Model (GLVM). To the best of our knowledge, this work has never been pub- lished in previous literatures. 2) Simulation results show that the hardware processing core achieves a 3.1 × 10 3 x in data throughput compared with the software approach using the C programming language. 2011 21st International Conference on Field Programmable Logic and Applications 978-0-7695-4529-5/11 $26.00 © 2011 IEEE DOI 10.1109/FPL.2011.19 44