1 DESIGN AND IMPLEMENTATION OF 32-BIT VEDIC MULTIPLIER ON FPGA Syed Shahzad Hussain Shah, Muhammad Naseem Majoka, and Gulistan Raja University of Engineering and Technology, Department of Electrical Engineering, Taxila, Pakistan sunnysyed08@yahoo.com, majoka.nasim2010@gmail.com, gulistan.raja@uettaxila.edu.pk Abstract. This paper describes the design and FPGA implementation of 32-bit Vedic multiplier. The proposed multiplier is designed to take two 32-bit inputs, and arranged each 32-bit input into two 16-bit blocks apply vertically and crosswise method on these blocks and arranges the partial products in a manner so they can be added using one carry save adder. The proposed architecture minimizes the combinational path delay which makes it more efficient. Simulation is done on ModelSim 5.7 simulator using Verilog HDL. Implementation is done on Spartan 3E FPGA, XC3S500 (device), FG320 (package),-5 (grade speed). Results of implementation show that the proposed architecture is faster than previous architectures of Vedic and non-Vedic multipliers. The maximum combinational path delay for proposed 32 bit multiplier is 22.829ns. Keywords: Carray Save Adder (CSA), Vedic, Vertically and Crosswise 1. Introduction Multiplication is a very essential arithmetic operation and extensively used in microprocessors, microcontrollers and digital signal processors. It is a time consuming operation because it takes more time and clock cycles as compared to other arithmetic operations. There are number of multiplication algorithms proposed in literature which include array, booth and Vedic algorithms. It is found from the various proposed architectures in literature that Vedic multipliers are faster than non-Vedic multiplier architectures [1-2]. Different architectures have been proposed in literature to improve the efficiency of multiplication using Vedic mathematics. These architectures are based on conventional Vedic, Vedic using RCA, Vedic using addition tree structure and Vedic using CSA. Gupta et al proposed architecture for conventional Vedic multiplier. The drawback of conventional Vedic architecture is that it works fine at 2 bit level but when we increase the order of multiplier, it becomes more complex [1]. Pushpalata and Mehta proposed an enhanced architecture for Vedic multiplier [2]. The drawback of this architecture is that it uses three stage ripple carry adders that increases combination path delay. Ganesh and Chrishma recently proposed a new architecture for Vedic multiplier using carry save adder (CSA) [3]. It uses carry save adders instead of ripple carry adders. The drawback of Vedic using CSA architecture is that it uses 2 carry save adders for adding partial products and second adder is not fully utilized. In this paper we propose a new architecture for Vedic multiplier which is more efficient in terms of both cost and speed. Rest of the paper is organized as follows: section 2 describes the overview of Vedic multipliers. Section 3 describes the proposed architecture for Vedic multiplier. Section 4 includes the simulations, implementation results and comparison. Section 5 is conclusion. 2. Overview of Vedic Multiplier Vedic multipliers are based on Vedic mathematics. Vedic mathematics has number of multiplication methods. The Urdhav-Triyakbhyam method is one of them. Urdhav-Triyakbhyam means “vertically and crosswise” [4-6]. This method is shown in Fig. 1. First International Conference on Modern Communication & Computing Technologies (MCCT'14) (Full Paper) 26-28 February, 2014, Nawabshah, Pakistan