A New Built-In Self-Test Approach for Digital-to-Analog and Analog-to-Digital Converters Karim ARABI, Bozena KAMINSKA and Janusz RZESZUT Department of Electrical and Computer engineering, École Polytechnique de Montréal P.O.Box 6079, Station Centre-Ville, Montréal, Québec, Canada H3C 3A7. Abstract This paper proposes a test approach and circuitry suitable for built-in self-test (BIST) of digital-to-analog (D/A) and analog-to-digital (A/D) converters. Offset, gain, linearity and differential linearity errors are tested without using test equipment. The proposed BIST structure decreases the test cost and test time. The BIST circuitry has been designed to D/A and A/D converters using CMOS 1.2 μm technology. By only a minor modification the test structure would be able to localize the fail situation. The small value of area overhead (AOH), the simplicity and efficiency of the proposed BIST architecture seem to be promising for manufacturing. Introduction Effective methods for testing the digital circuitry are known, but testing the analog circuitry is still a problem. A great deal of effort has been devoted to testing pure analog circuits [3],[5]. Approaches for designing testable analog and mixed circuits have also been reported [6],[8], but up to now there is no general and efficient solution. The most frequently encountered parts of mixed digital and analog circuits are digital-to-analog (D/A) and analog-to-digital (A/D) converters, which bridge the gap between digital and analog systems. Many articles have been published about the design, specification and applications of D/A converters. Unfortunately, little has been written about testing conversion products [2] that need expensive mixed-signal test equipment. Appropriate BIST methods solve these problems, because test equipment is not needed. The goal of this work is to propose an optimized BIST approach to automatically test the linearity and differential linearity errors, offset voltage (V OSE ) and gain error (G FSE ) of D/A converters. Then, the same BIST approach is mapped to A/D converter testing. A BIST Scheme for D/A Converters The area overhead (AOH) is one of the most essential problem of the analog BIST approaches. In order to reduce the AOH, the proposed BIST structure does not use a reference D/A converter that normally has 3 to 4 more bits of resolution, as presented in previous works [2],[4]. A. BIST Architecture for D/A Converter Testing Fig. 1 illustrates the proposed approach for testing some static characteristics of a D/A converter in order to verify its functionality. When the Test input becomes active, the control logic (CL) begins the test procedure and directs the operation of the counter, D/A converter, analog switches and analog multiplexer (AMUX), and observes the output of the comparator. This BIST structure tests V OSE , differential linearity, ε i,i-1 , at all 2 N input codes, G FSE , and linearity, ε i , at 7 critical values. They are measured as follows: V OSE = V O (00...0) - GND (1) G FSE = V O (11...1) + 1 LSB - V REF (2) ε i,i-1 = V O (i) - V o (i-1) - 1 LSB (3) ε i = V O (i) - (b 1 2 -1 +b 2 2 -2 + ...+b N 2 -N )×V REF (4) where i = (b 1 b 2 b 3 ...b N ) The measured parameters are alternately compared with values 1/2 LSB and -1/2 LSB (or maximum acceptable tolerance margin) to verify whether or not they are smaller than the maximum allowance error voltage. B. Autozeroing Technique During autozero cycle (AZC), AZ is active and AMUX selects GND. Thus, operational amplifier (OA) is connected in the unity gain configuration and the input offset is available at the output. Capacitor C AZ stores the offset across its terminals. After applying the offset- cancellation algorithm, C AZ is placed in series with V OS at the noninverting input of the OA to cancel the existing offset voltage. The idea of offset-cancellation offers the possibility of automatically nulling the offset voltage without using external pins. C. Test procedure When the Test input becomes active, the control logic performs a self testing to verify the functionality of the test circuitry. Then, it begins the D/A converter testing. The test algorithm consists of the following phases: