HIGH POWER, HIGH EFFICIENCY, LOW COST CAPACITOR CHARGER
CONCEPT AND DEMONSTRATION
A. Pokryvailo
ξ
, C. Carp and C. Scapellati
Spellman High Voltage Electronics Corporation, 475 Wireless Boulevard
Hauppauge, NY 11788
ξ
email: Apokryva@spellmanhv.com
Abstract
A 20-kJ/s, 10-kV, 1-kHz repetition-rate technology
demonstrator design and testing are described. The goal of
the development was combining high performance and
versatility with low-cost design and good
manufacturability. This goal was met using an energy-
dosing converter topology with smart controls adapting
the switching frequency in such a way as to ensure zero-
current switching for all possible scenarios, keeping
maximum duty cycle for high power. The switching is
accomplished at a frequency of up to 55 kHz employing
relatively slow IGBTs with low conduction losses. High
efficiency allows all-air cooled design that fits into a
19”x10”x24” rack.
Design guidelines are reviewed. Comprehensive PSpice
models accounting for numerous parasitic parameters and
mimicking controls for the frequency variation were
developed, and simulation results are presented. Together
with analytical tools, they predicted a pulse-to-pulse
repeatability (PPR) of ±0.15 %; the measured figures are
±0.4 % and ±0.5 % for short- and long-term operation,
respectively, at peak charging and repetition rate.
Repeatability analysis is briefed upon here, and to larger
extent, in an accompanying paper. Test methods are
described. Typical current and voltage traces and results
of thermal runs are presented.
I. INTRODUCTION
Between numerous capacitor charging applications, a
combination of high voltage, high charging rate (tens of
kJ/s and higher), high pulse repetition rate (PRR),
compactness, high efficiency and good pulse-to-pulse
repeatability (PPR) is a serious technological challenge.
Putting constraints of low-cost and good
manufacturability makes the charger development even
more difficult. They restrict use of costly switches, e.g.,
SiC, exotic cooling schemes and materials, leaving
freedom to choose proper circuit topology and control
strategy to increase the switching frequency with the
purpose of shrinking the size and improving PPR. This
paper describes an attempt to satisfy the above
contradicting requirements within the constraints of low-
cost proven technology.
II. MAIN SPECIFICATIONS
Input Voltage
400 VAC or
% 10
% 14
480
+
−
VAC , 3Φ
50/60 Hz, frequency % 2 ±
Output Voltage 0÷10 kV
Average
Charging Rate
20 kJ/s
PRR Single shot to 1 kHz
Efficiency >92 % at full charging rate, >85 %
at 30 % of rated power
Power factor >0.93 at full charging rate
>0.85 at 30 % of rated power
Pulse to Pulse
repeatability
Better than % 5 . 0 ± at 1 kHz,
10 kV, full power; long-term
Better than % 4 . 0 ± at 1 kHz, 10 kV,
full power; short-term
Better than % 1 ± at 1 kHz, 2 kV-
10 kV, short-term.
Insulation Air, 10 kV and below
Size 10½” (6U)H x 19”W x 24”D
rack mount
Weight 90 lb (41 kg)
Cooling Air
III. DESIGN
A charger block-diagram is shown in Figure 1. The
charger comprises a 3-phase input rectifier with soft start
and a smoothing filter, a converter module (CM), an HV
divider and control means. Triggered by an external
source, the charger charges capacitor Cs that is discharged
onto a dummy load via a high-power switch DSw.
CM comprises an inverter INV, HV transformer using
popular U100/57/25 ferrites, a rectifier R and control
means. The CM’s heart is a half-bridge quasi-resonant
inverter with energy dosing capacitors (Figure 2) [1]-[3].
Work [2] provides the principle and theory of operation.
The benefits of this topology are tight control of the
energy transfer and inherent limitation of the short circuit
current and voltages across the converter components.
The maximum conversion frequency is 55 kHz at low
rail voltage. The parasitics of the HV transformer together
with capacitors Cdiv form the resonant tank circuit.
801 9781-4244-4065-8/09/$25.00 ©2009 IEEE
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