Controlling STI-related parasitic conduction in 90 nm CMOS and below E.Augendre, R.Rooyackers, D.Shamiryan, C.Ravit * , M.Jurczak and G.Badenes IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium * Philips Research Leuven, Kapeldreef 75, 3001 Leuven, Belgium E-mail: augendre@imec.be Abstract In parallel to its continuous scaling, shallow trench isolation (STI) requires thorough optimisation with respect to its impact on device performance. In particular, the conduction occurring at the isolation edge of the device needs to be limited. Among the factors that influence the related control of threshold voltage and subthreshold current, this paper evaluates the impact of process parameters such as transistor architecture, trench profile (conventional or T-shape) and, for the first time, sacrificial oxidation strategy. It is first proven that conventional STI architecture can provide the same gate oxide integrity and control of lateral conduction as T-shape STI. Second, it is shown that transistor scaling improves immunity to narrow channel effects. This is illustrated with an optimised conventional STI module showing hump-free operation and threshold voltage variation of 40 mV down to 0.11 μm wide nMOS transistors, making the approach suitable at least down to the 90 nm technology node. 1. Introduction STI is the only lateral isolation scheme that meets the requirements of deep sub-micron technologies in terms of active area scaling and topography at gate level. For each technology node, trench patterning and filling need adjustment towards the design rules. At the same time, significant optimisation efforts go to the tailoring of silicon and oxide profiles at the edge of active area in order to control both gate oxide integrity and device off-state current. In that respect, it is essential that the silicon corner is rounded and that the neighbouring trench oxide shows minimum recess, preventing the gate from wrapping around the silicon corner. These avoid field crowding that locally lowers the threshold voltage and results in a parasitic leakage path along the lateral transistor [1]. Silicon corner rounding is commonly achieved via high temperature oxidation of the trench sidewalls [2]. Preventing gate wrap-around is more problematic since significant oxide recess is likely to originate from all (isotropic) HF oxide etch steps that are carried out between the post-planarisation nitride etch and gate stack deposition. Several methods were proposed to limit gate wrap- around with STI, based on the covering of active area edge with a thick oxide (e.g. by forming a bird’s beak [3] or a T-shaped trench [4]). This thick oxide delays the formation of the lateral oxide recess, but it also impacts effective channel width and can introduce non- uniformities due to the added pattern density dependence of T-shape formation. In this paper, we present for the first time the complementary approach that consists in drastically limiting the amount of critical HF oxide etch steps, with no negative draw-back on channel width or pattern uniformity. Part 2 gives processing details, part 3 compares this approach to T-shape STI in terms of morphology, gate oxide integrity and transistor behaviour and part 4 demonstrates the interest of such an approach down to at least the 90 nm CMOS node. 2. Experimental Processing started with the formation of active area stack (15 nm pad oxide and 150 nm nitride). After printing using 193 nm lithography, 400 nm, 325 nm and 250 nm-deep trenches were etched in the silicon. A conventional straight STI profile is achieved by two-step etching: nitride etching is immediately followed by silicon trench etching with the same resist mask. In some of the 400 nm samples, an additional etch step was inserted after nitride etching to obtain T-shape STI. This step uses highly polymerising chemistry that intentionally creates polymers on the nitride sidewalls. These polymers are masking the subsequent trench etching, producing an offset between nitride and silicon sidewalls [4] (although in contrast to reference [4], polymerisation was here decoupled from silicon etching, resulting in an almost horizontal top silicon surface). After stripping, all samples underwent the same high temperature sidewall oxidation that rounded silicon corners and trenches were filled with high-density plasma (HDP) oxide. Samples that had received polymerising showed a T-shape oxide profile, with HDP oxide covering the edges of active area. Next, all wafers received dummy-free planarisation [5] and nitride was etched away.