2492 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005 A Fully Integrated SOC for 802.11b in 0.18- m CMOS Shahla Khorram, Hooman Darabi, Senior Member, IEEE, Zhimin Zhou, Qiang (Tom) Li, Member, IEEE, Bojko Marholev, Janice Chiu, J. Castaneda, Hung-Ming (Ed) Chien, Seema Butala Anand, Stephen Wu, Meng-An Pan, Razieh Roofougaran, Hea Joung Kim, Paul Lettieri, Brima Ibrahim, Jacob J. Rael, Member, IEEE, Long H. Tran, E. Geronaga, H. Yeh, T. Frost, J. Trachewsky, and Ahmadreza Rofougaran, Senior Member, IEEE Abstract—A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18- m CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access con- trol (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and 88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range. Index Terms—CMOS integrated circuits, demodulation, direct conversion, frequency synthesizers, IEEE 802.11b, mixers, phase and frequency modulation, power amplifier (PA), radio trans- ceivers, receiver, spread-spectrum communication, transmitter, wireless local area network (WLAN). I. INTRODUCTION T HE IEEE 802.11b standard provides a high bandwidth to the users in a local area network (LAN) such as in a building or inside an office [1]. The data are modulated by binary phase-shift keying (BPSK), quaternary phase-shift keying (QPSK), or complimentary code keying (CCK) and further mapped by a direct-sequence spread-spectrum (DSSS) technique. It supports a data rate of up to 11 Mb/s and consists of three nonoverlapping channels in the 2.4-GHz industrial, scientific, and medical (ISM) band in the United States. An 802.11b device must satisfy certain requirements. It should be small and low cost to integrate with notebook computers and other portable devices efficiently, and yet it must have a robust performance to function properly along with the interferers. Such interferers exist in a noisy radio frequency (RF) environ- ment in which several powerful radio signals are present in the proximity of the radio, such as global system for mobile com- munications (GSM) or code division multiple access (CDMA) signals. The following paper presents a radio architecture, as well as various circuit techniques to realize a low-power and highly integrated transceiver in 0.18- m CMOS capable of supporting the 802.11b standard. The CMOS system-on-a-chip (SOC) integrates all of the radio building blocks as well as the physical layer and medium access control (MAC) sections into Manuscript received April 26, 2005; revised July 15, 2005. The authors are with the Broadcom Corporation, Irvine, CA 92618 USA (e-mail: hdarabi@broadcom.com). Digital Object Identifier 10.1109/JSSC.2005.857419 a single chip, providing a low-cost solution for high-volume wireless local area network (WLAN) products. The cost is further reduced by integrating most of the external components such as antenna transmit/receive (T/R) switch, power amplifier (PA), and RF baluns. Although the baseband and MAC sections are intended to support the 802.11b standard, the radio is capable of supporting 802.11g requirements without any change required except for the need for an external PA. This is due to the more stingent requirement on the transmitter 1-dB compression point. Other- wise, the other key parameters, such as the radio noise figure, and matching, as well as phase noise performance meet the 802.11g requirements. In Section II, the system considerations are discussed, and the proposed transceiver architecture is presented. Section III de- scribes the circuit details of some of the transceiver key building blocks, including the PA, and the T/R switch. In Section IV, the single-chip integration issues are discussed, and, finally, in Sec- tion V, the measurement results are presented. II. TRANSCEIVER ARCHITECTURE A block diagram of the CMOS transceiver, employing a di- rect-conversion architecture is shown in Fig. 1. In the receive path, an on-chip low-noise amplifier (LNA) with single-ended input boosts the incoming signal. The signal is down-converted by quadrature Gilbert-type active mixers. The analog baseband section consists of an active-resistance–capacitance (RC) low- pass filter (LPF) with 3-dB bandwidth of about 8 MHz, fol- lowed by a programmable gain amplifier (PGA). The outputs of the and PGAs are digitized by a ping pong 8-b pipelined analog-to-digital converter (ADC) with an aggregate clock rate of 88 MHz. A received signal strength indicator (RSSI) esti- mates the desired input power, required for gain control pur- poses. In addition, a wideband RSSI before the channel-select filters is used to estimate the blocker level, and to adjust the LNA gain proportionally. The analog outputs of the RSSI blocks are multiplexed into a 6-b flash ADC clocked at 44 MHz. The transmitter takes and signals from two 8-b cur- rent steering digital-to-analog converters (DACs) clocked at 88 MHz. It consists of and LPFs that reject the data converter image frequency, followed by single sideband (SSB) up-conversion mixers. The mixer output signal is boosted by a preamplifier stage that delivers the required swing to the PA and provides the gain control for the transmit path. The PA is a linear class AB stage loaded by an on-chip transformer to drive 0018-9200/$20.00 © 2005 IEEE