Abstract - State assignment for finite state machines is a criti- cal optimization problem in the synthesis of sequential circuits. In this paper we address the state assignment problem from a low power perspective. We experiment with Boolean Satisfiabili- ty and Integer Linear Programming techniques to solve the as- signment problem where the primary goal is the reduction of switching activity during state transitions. We also detect and evaluate the use of symmetries in speeding up the search process. These techniques have been applied to the MCNC benchmark circuits and yielded promising results. Keywords - State Assignment, Power, Integer Linear Program- ming, Boolean Satisfiability I. INTRODUCTION With the ever increasing integration scale, power con- sumption has emerged as a major design constraint for inte- grated circuits. During logic synthesis of sequential circuits, i.e. finite state machines (FSMs), assigning binary codes to each state in the circuit is a critical step in the low power de- sign of the circuit. The state encoding problem for low power has been explored by a number of researchers. Recent work has attempted to address this issue using various techniques. In [7], using a probabilistic description of the circuit, a state assignment algorithm that minimizes the Boolean distance be- tween the codes of the state with high transition probability was proposed. The primary objective was to reduce the aver- age switching activity of the input and output state variables by minimizing the number of bit changes during state transi- tion. Symbolic methods for re-encoding a circuit to reduce the dissipated power are discussed in [17]. The authors experi- mented with two encoding strategies. One based on recursive weighted no-bipartite matching, and one on recursive mincut bi-partitioning. The authors conclude that even though the re- sults are promising, their synthesis procedure needs refine- ments in both circuit transformation and the power estimation phases. Encoding of states for a given user-specified input se- quence was addressed in [18]. Simulation was used to deter- mine the relative frequency for all state transitions. By defining and using a register switching rate as a cost, the au- thors then used simulated annealing to solve the state assign- ment problem. In [12], given an FSM description and the input probabilities, the total state transition probabilities for each edge in a state transition graph of the circuit are computed first. This is done by modeling the FSM as a Markov chain. A cost function that is the summation of the products of distinct code words with the Hamming distance between any two ad- jacent states is used to measure the effectiveness of the assign- ments. Similar to [7], the goal is to assign codewords with minimum Hamming distances to states with higher transition probabilities. A spanning tree based encoding approach was tested in [25]. The assignment problem was formulated as a hypercube embedding problem, where the embedding process is directed by a maximum spanning tree of the attraction graph of the FSM. In [6], heuristic techniques were used to visit the state transition graph of the circuit and assign a priority to the symbolic states. Next, an encoding technique that follows the priority established in the first part is used to assign binary codes to the states. As assignment method that utilized dy- namic loop information extracted from FSM profiling data was presented in [16]. The authors then experimented with three different loop-based state assignment algorithms, depth- first search, loop-based depth first and per state encoding. An m-block partitioning technique for the state assignment to re- duce the number of feedback cycles and keep low switching activities among state variables is discussed in [26]. The ob- jective was both, to improve power consumption and testabil- ity of the circuit. Re-engineering (targeting low power) an FSM by constructing a functionally equivalent but topologi- cally different design based on an optimization objective was presented in [31]. The authors argue that this will allow the ex- ploration of a larger solution space making it possible to ob- tain solutions better than the optimal ones for the original circuit. They used genetic algorithms and heuristics to re-en- gineer existing low power state encoding procedures with fa- vorable results. The last decade have seen a remarkable growth in the use of Boolean Satisfiability (SAT) models and algorithms for solving various problems in Electronic Design Automation (EDA). This is mainly due to the fact that SAT algorithms have seen tremendous improvements in the last few years, al- lowing larger problem instances to be solved in different ap- plications domains [5, 8, 22, 27]. Such applications include formal verification [9], FPGA routing [23], global routing [4], logic synthesis [21], and power optimization [28]. Low Power State Assignment Using ILP Techniques Assim Sagahyroon #1 , Fadi A. Aloul #2 , Alexander Sudnitson *3 # Department of Computer Science & Engineering, American University of Sharjah, UAE 1 asagahyroon@aus.edu 2 faloul@aus.edu * Department of Computer Engineering Tallinn University of Technology, Estonia 3 alsu@cc.ttu.ee