Cu Nanolines for Application in RF Interconnects Panagiotis Sarafis 1 , Philippe Benech 2 , Androula G. Nassiopoulou 1* 1 NCSR Demokritos/IMEL, Terma Patriarchou Grigoriou, Aghia Paraskevi, 153 10 Athens, Greece 2 IMEP-LAHC, Grenoble Universite, 3 Parvis Louis Neel, CS 50257, Grenoble Cedex 38016, France *Corresponding author’s e-mail: A.Nassiopoulou@imel.demokritos.gr Abstract— According to the ITRS the dimensions of the lower interconnect lines are expected to be reduced below 25nm for the years after 2014. In this work we investigate the properties of Cu nanolines in coplanar waveguide transmission line (CPW TLine) configuration for their potential use as RF interconnects in analog applications using the lower metal layers of the back-end-of-line (BEOL) CMOS processes. The Cu nanolines had a thickness of 100nm and a width ranging from 50nm to 1ȝm and they were patterned using electron beam lithography and lift-off. The nanolines were characterized in the frequency range 1-40 GHz. Extra attention was paid to the de-embedding procedure and the extraction of the properties of the intrinsic Cu nanoline. Finally, the results were compared with those obtained from electromagnetic simulations. Keywords- Copper, nanolines, RF, co-planar waveguides, de-embedding I. INTRODUCTION It is well known that the CMOS technology evolves through scaling down of the transistor dimensions. This improves the performance of the transistor and reduces the power consumption of the integrated circuit (IC). In order to fulfill the needs of the continuous scaling down, the interconnect lines should also scale down. In the latest CMOS technologies the dimensions of the interconnect lines are pushed down below 50 nm. According to ITRS 2011 [1] it is predicted that the width of local interconnects will be reduced to 30 nm in 2017. This size reduction compromises interconnect line performance [2]. It is well known that Cu resistivity increases and the allowed current density decreases when the line cross-section decreases [3]. To overcome these bottlenecks, a lot of effort is put into finding alternative materials to replace Cu [4]. Most of the undergoing research go into the investigation of bundles of carbon nanotubes (CNTs), because as they have reduced resistivity and increased electromigration immunity [5]. However, the application of CNTs in CMOS technology is not so prominent and it still remains challenging due to non compatibility with CMOS processing [6]. This is the reason why the investigation of Cu nanolines with dimensions approaching those of the lower CMOS metallization layers i.e. thin (~ 100 nm) and narrow (< 200 nm) lines is still interesting. The resistivity of Cu nanolines has been investigated during the previous decade [7]. However, only few papers were devoted to the RF properties of nanoscaled Cu and other metal nanolines [8]–[11] . In this work we examine the RF properties of different Cu nanolines with linewidth from 50 nm to 1 ȝm and line thickness equal to 100nm. This is a typical dimension for the interconnect lines of the lower layers of the back-end- of-line (BEOL) [1]. The nanolines were fabricated on a thick porous Si layer which was demonstrated to provide the necessary RF isolation from the silicon substrate [12]. The nanolines were characterized up to 40 GHz and the results were compared to those obtained using full-wave EM simulations. II. FABRICATION A. Substrate In order to decouple the performance of the Cu nanolines from the substrate, we have to use a substrate that does not introduce losses to the electromagnetic wave propagation. A thick porous Si layer on the Si wafer has been shown to provide excellent shielding from the substrate in the whole frequency range from dc to mm-wave frequencies [12-15]. Porous Si eliminates parasitic surface conduction and thus the substrate effects are decoupled. The specific porous Si layer used in this work had a porosity of 72%, a relative permittivity İ r ~3.5 and a loss tangent tanį=0.03. B. Copper Nanolines The devices-under-test included both DC and RF test structures. The DC structures were used to measure the resistivity of the Cu nanolines. The RF test structures were CPW TLines with the Cu nanoline as the signal line. The devices were fabricated using e-beam lithography followed by Cu deposition by electron gun evaporation and lift-off. The metal pads were made of the same 100nm thick Cu metal layer and were fabricated in the same process step as the nanolines. This assures that there is no contact resistance between 978-1-4799-3718-9/14/$31.00 ©2014 IEEE 149