Impact of the on-chip and off-chip ESD protection network on transient-induced latch-up in CMOS IC Mirko Scholz (1), Shih-Hung Chen, Geert Hellings, Dimitri Linten imec, Kapeldreef 75, B-3001 Leuven, Belgium; email: mirko.scholz@imec.be (1) also at: Vrije Universiteit Brussels, Dept. ELEC, Brussels, Belgium Abstract – Measurements and mixed-mode simulations are used for the analysis of transient-induced latch-up (TLU) in CMOS IC. The transient interaction of the parasitic SCR with the surrounding off-chip and on-chip circuitry is investigated during positive and negative system-level ESD stress. It is shown, that sufficient on- chip decoupling and an active clamp can improve the TLU robustness of a circuit. I. Introduction The application of system-level ESD stress to devices and integrated circuits (IC) has received lots of attention in the recent years. In addition to the component-level ESD requirements, electronic products are required to pass e.g. the specifications of the IEC61000-4-2 system-level ESD standard. A qualified product needs to be functional both under power-off and power-on conditions when applying system-level ESD stress to it. This adds some additional challenges to the component-level ESD protection design. No critical conduction paths or even transient-induced latch-up (TLU) may occur when the IC is powered up. TLU is triggered by transient pulses which have a much shorter rise time and duration than a static latch- up test [1, 2]. As a consequence, the risk for TLU is often not detected during the static JEDEC latch-up test [2]. For instance, system-level ESD stress can cause over-voltages and current injection which exceeds the specifications of the JEDEC latch-up test. The rise time of the system-level ESD stress current is usually in the sub-nanosecond range and much larger stress amplitudes are applied. This can trigger different parasitic structures in the powered-up IC than during a JEDEC latch-up test. Because of this, many TLU failures during system-level ESD testing have been reported [2, 3]. This work investigates how the off-chip and on-chip ESD protection design impacts the TLU sensitivity of a CMOS IC during system-level ESD stress. Measurements and simulations are used for the analysis. The presented simulation setup combines TCAD, compact and SPICE modeling. The analysis provides new insights on the transient interaction between the parasitic SCR and the off-chip and on- chip ESD protection circuitry. It is shown how the risk for TLU in an IC can be analyzed already early during the design phase. II. Test case and measurements This work simulates a latch-up sensitive IC which is protected by an off-chip protection network (Figure 1). Its power supply is decoupled off-chip with three decoupling capacitors of different values. The values are chosen based on the typical decoupling networks used in many application boards. Figure 1: Schematic of test case: V ESD – ESD stress source (HMM tester), V DD – supply voltage, C x – off-chip decoupling capacitors with parasitic, TVS – TVS diode for 3.3 V applications The test case consists of a SCR which represents a parasitic SCR in a CMOS circuit manufactured in a 130 nm technology. The SCR triggers around 15.5 V. This high trigger voltage prevents that the SCR turns on during a static latch-up test [2] where an overvoltage of 50 % above the supply voltage of 3.3 V is applied to the circuit. An active clamp is used as on-chip power clamp. It represents the most common supply pin ESD