System-level ESD protection of high-voltage tolerant IC pins – A case study Mirko Scholz 1 , Steven Thijs, Shih-Hung Chen 2 , Alessio Griffoni, Dimitri Linten, Masanori Sawada 3 , Gerd Vandersteen 1 , Guido Groeseneken 2 imec, Kapeldreef 75, 3001 Leuven, Belgium (1) also at: Vrije Universiteit Brussels, Dept. ELEC, Brussels, Belgium; (2) also at: Katholieke Universiteit Leuven, Dept. ESAT, Leuven, Belgium; (3) HANWA Electronics Ltd., Wakayama, Japan email: mirko.scholz@imec.be Zusammenfassung – Mit und ohne anliegende Versorgungsspannung wurde eine Systemebene-ESD Schutzlösung für HVT IC-Pins untersucht. Die transiente Wechselwirkung des untersuchten SCRs mit den Komponenten auf Systemebene muss sorgfältig geprüft werden, um einen thermischen Ausfall des SCR zu verhindern, wenn keine Versorgungsspannung angelegt ist und Latchup, wenn der SCR eingeschaltet ist. Abstract – A system-level ESD protection solution for HVT IC pins is studied without and with applied supply voltage. The transient interaction of the studied SCR with the off-chip components needs to be studied carefully to prevent a thermal failure of the SCR when no V DD is applied and latchup when the SCR is powered up. 1 Introduction Integrating high-voltage (HVT) circuitry into a standard low-voltage CMOS process is one of the challenging tasks when System-on-chip (SOC) solutions like line drivers, USB interfaces, display drivers etc are implemented. These HV-tolerant (HVT) IC pins operate at higher supply voltages (V DD ) then the used low-voltage technology. Due to the higher V DD the classical ESD protection solutions of the used low-voltage process often do not work. Moreover additional challenges can occur. For example, due to the higher V DD there is a higher risk for latch up when the circuit is powered up. In this paper, we demonstrate a system-level ESD protection methodology for HVT IC pins using a test board and board-level components together with an on-chip protection device on-wafer. With measurements and simulations the interaction between on-chip and off-chip devices is analyzed. The presented methodology enables the study of on-chip ESD protection devices under system- level ESD stress conditions and their interaction with board-level components even before IC packaging. First, we present the test structure and measurement setup. In the following section the protection methodology for the non-powered state is demonstrated. Next we show how to protect the selected test structure for the case that a supply voltage is applied to it, followed by some conclusions. 2 Test structure, test board and measurement setup To study the system-level ESD robustness of HVT IC pins a standard Silicon-Controlled Rectifier (SCR), manufactured in a 130 nm CMOS technology, has been selected. The nominal supply voltages in this technology are 1.2 V and 3.3 V. Due to its high trigger voltage (~ 15.5 V) during ESD stress and the absence of a gate oxide it can be safely used as an ESD protection for HVT circuitry. Due to their known latchup sensitivity SCRs are usually not used as a standalone power clamp. In this study we use the SCR as a “latchup monitor” and thereby working as a replacement for a latchup sensitive circuit in a real application. The SCR used is measured on-wafer. The probe needles and probe holder parasitic are extracted beforehand [1] and included in the analysis to determine the influence of the needle parasitic in the setup during ESD stress. Off-chip components are added to the SCR by connecting a dedicated double layer test board (Figure 1) to the on-wafer setup. The test board has been manufactured using an industrial PCB process and FR4 as board