Electrical Properties of Pulsed Laser Deposited Y
2
O
3
Gate
Oxide on 4H–SiC
Hock Jin Quah,
a
Way Foong Lim,
a
Stuart C. Wimbush,
b
Zainovia Lockman,
a
and Kuan Yew Cheong
a,z
a
Energy Efficient and Sustainable Semiconductor Research Group, School of Materials and Mineral
Resources Engineering, Universiti Sains Malaysia, Engineering Campus, 14300 Nibong Tebal, Pulau Pinang,
Malaysia
b
Department of Materials Science and Metallurgy, University of Cambridge, Cambridge CB2 3QZ, United
Kingdom
Yttrium oxide Y
2
O
3
has been successfully deposited on n-type 4H–SiC substrates using pulsed laser deposition. The effects of
postdeposition annealing temperature 400, 500, and 600°C on the electrical properties of the Y
2
O
3
gate oxide have been studied
in comparison with the as-deposited sample. The sample annealed at 600°C possessed the highest dielectric breakdown field of
6.5 MV cm
-1
at 10
-6
A cm
-2
, resulting from the lowest interface trap density and total interface trap density. The Fowler–
Nordheim tunneling mechanism has been investigated on all samples and the highest value of barrier height extracted between the
semiconductor and oxide conduction band edges was 2.67 eV.
© 2010 The Electrochemical Society. DOI: 10.1149/1.3481926 All rights reserved.
Manuscript submitted July 8, 2010; revised manuscript received July 28, 2010. Published September 3, 2010.
Tremendous research effort has been focused on the utilization of
wide bandgap WBG semiconductors as substrates for high power
metal oxide semiconductor MOS based devices due to their im-
pressive properties. Among the WBG semiconductors, silicon car-
bide SiC with its high breakdown field E
B
, high electron drift
velocity, and high thermal conductivity has been suggested as a
suitable substrate for the aforementioned application.
1,2
The integra-
tion of a high quality gate oxide is essential in SiC-based MOS
devices to prevent the injection of charge from the SiC or the gate
electrode, thus sustaining a high E
B
and a low gate leakage current.
3
The exceptional advantage of SiC when compared with other WBGs
is its ability to produce a native oxide SiO
2
via thermal
oxidation.
1,4
To date, thermally nitrided SiO
2
on SiC is regarded as
the most promising gate oxide due to its exhibition of an extremely
low leakage current.
5-7
However, its relatively low dielectric con-
stant
SiO
2
= 3.9 when compared to that of SiC
SiC
= 9.7 may
constrain the maximum permissible electric field.
8,9
Therefore, the
application of high- gate oxides such as Al
2
O
3
,
10
CeO
2
,
9
La
2
O
3
,
11
HfO
2
,
12
and Gd
2
O
3
13
on SiC substrates has been thoroughly inves-
tigated to enable the exploitation of the SiC breakdown field. Yt-
trium oxide Y
2
O
3
is a potential candidate as an alternative gate
oxide for SiO
2
due to its relatively high- value = 14–18, large
bandgap 5.5 eV, and high thermal stability of up to 2300°C.
14,15
However, there is no article on utilizing Y
2
O
3
as the gate oxide for
SiC MOS-based devices. Thus, the effects of postdeposition anneal-
ing on the MOS characteristics of a pulsed laser deposited Y
2
O
3
film on SiC have been systematically investigated in this work.
Experimental
n-Type, 8° off 0001 oriented, 4H–SiC wafers with a 10 m
thick epilayer doped with 1–4 10
16
cm
-3
of nitrogen were used
as the starting substrates. The SiC wafer was subjected to the RCA
cleaning process, and the native oxide of SiO
2
was etched by
HF:H
2
O 1:50 solution. Y
2
O
3
films with a thickness of 20 nm
were deposited on these substrates by off-axis pulsed laser deposi-
tion KrF of = 248 nm, 10 Hz, 2 J cm
-2
in an oxygen atmo-
sphere 30 Pa to maintain oxygen stoichiometry, in which the thick-
ness was measured by in situ growth process. The substrates were
held at 800°C during deposition and subsequently cooled at
30°C /min in 0.5 atm static oxygen. After the deposition, an ex situ
postdeposition annealing treatment was performed at different tem-
peratures 400, 500, and 600°C in argon atmosphere for 15 min.
The heating and cooling rates were 5°C /min. A typical field-
emission-scanning electron microscopy FESEM micrograph inset
of Fig. 1 reveals that the produced film is smooth and uniform,
while energy-dispersive X-ray spectroscopy not shown performed
at six different locations showed that Y
2
O
3
is homogenously distrib-
uted through the film with an atomic percentage of Y and O of
0.97 0.05 and 1.46 0.15 atom %, respectively. Thus, the re-
sulting film achieved a stoichiometric of Y:O = 2:3. After cooling, a
layer of Al was thermally evaporated on top of the oxide. An array
of 2.5 10
-3
cm
2
Al gate electrodes was then defined using a pho-
tolithography process. Electrical properties of the test structures
were examined by high frequency 1 MHz capacitance–voltage
C-V and current–voltage measurements using an LCR meter Agi-
lent 4284A and a semiconductor parameter analyzer Agilent
4156C, respectively.
Results and Discussion
Figure 1 presents the high frequency normalized C-V curves of
the as-deposited and annealed Y
2
O
3
films at different temperatures,
in which the gate bias is swept bidirectionally from -4 to +4 V.
Negative flatband voltage shift V
FB
is observed in both the 400 and
500°C annealed samples, implying that positive traps are present in
these samples. A larger negative V
FB
is exhibited by the sample
z
E-mail: cheong@eng.usm.my
Figure 1. 1 MHz normalized C-V curves for the as-deposited and annealed
Y
2
O
3
gate oxides on SiC same symbols used in this figure apply to the
following figures. The inset shows a typical FESEM micrograph of Y
2
O
3
film annealed at 600°C.
Electrochemical and Solid-State Letters, 13 11 H396-H398 2010
1099-0062/2010/1311/H396/3/$28.00 © The Electrochemical Society
H396
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