IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 12, DECEMBER 2009 3149 New Ballasting Layout Schemes to Improve ESD Robustness of I/O Buffers in Fully Silicided CMOS Process Ming-Dou Ker, Fellow, IEEE, Wen-Yi Chen, Student Member, IEEE, Wuu-Trong Shieh, and I-Ju Wei Abstract—Silicidation has been reported to result in substantial negative impact on the electrostatic discharge (ESD) robustness of MOS field-effect transistors. Although silicide blocking (SB) is a useful method to alleviate ESD degradation from silicidation, it re- quires additional mask and process steps to somehow increase the fabrication cost. In this paper, two new ballasting layout schemes to effectively improve the ESD robustness of input/output (I/O) buffers with fully silicided NMOS and PMOS transistors have been proposed. Ballasting technique in layout is a cost-effective method to enhance the ESD robustness of fully silicided devices. Experimental results from real IC products have confirmed that the new ballasting layout schemes can successfully increase the HBM ESD robustness of fully silicided I/O buffers from the origi- nal 1.5 kV to over 6 kV without using the additional SB mask. Index Terms—Ballast resistance, electrostatic discharge (ESD), ESD protection, input/output (I/O) buffer, silicidation. I. I NTRODUCTION T O INCREASE the driving capability and maximum operating frequencies of MOS field-effect transistors (MOSFETs), silicidation has been widely adopted in chip fabri- cations since deep-submicrometer CMOS era. In the fully sili- cided CMOS technologies, the silicidation is typically carried out through metallurgical reaction between silicon and pre- deposited silicide metals (titanium, cobalt, or nickel) [1]–[3]. With proper annealing steps, refractory metal silicides are formed to provide a low resistivity for the diffusions and polysilicon gates of MOSFETs. Although the low resistivity from silicides is advanta- geous to the driving capability and operating frequencies of MOSFETs, it has been reported that silicidation induces electrostatic discharge (ESD) degradation due to the current crowding within the shallow surface [4]–[6]. Moreover, the Manuscript received July 2, 2009; revised August 13, 2009. First pub- lished October 30, 2009; current version published November 20, 2009. This work was supported in part by ELAN Microelectronics Corporation, Hsinchu, Taiwan, by the Ministry of Economic Affairs, Taiwan, under Grant 97-EC-17- A-01-S1-104, and by the “Aim for the Top University Plan” of the National Chiao Tung University and the Ministry of Education, Taiwan. The review of this paper was arranged by Editor C. Jungemann. M.-D. Ker is with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan, and also with the Department of Electronic Engineering, I-Shou University, Kaohsiung County 84001, Taiwan (e-mail: mdker@ieee.org). W.-Y. Chen is with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan. W.-T. Shieh and I-J. Wei are with ELAN Microelectronics Corporation, Hsinchu 30076, Taiwan. Digital Object Identifier 10.1109/TED.2009.2031003 bend-down of silicidation located near the shallow trench isolation (STI) corner leads to the deterioration of the ESD robustness of fully silicided devices [7]. Owing to these effects during ESD stresses, silicidation has been confirmed to result in precipitous degradation on the ESD protection levels of CMOS ICs in advanced CMOS technologies. To recover the silicidation-induced degradation on ESD ro- bustness, CMOS processes with additional silicide blocking (SB) have been proposed [8]–[14]. Because the temperature for silicon dioxide (SiO 2 ) to form metallurgical silicides is higher than that for silicon, SB can be achieved by depositing sacrificial oxide on the selected regions before the deposition of silicide metal. The sacrificial oxide therefore separates the contact between silicon and the silicide metal, preventing these selected regions from silicidation during the subsequent anneal- ing processes. By using the SB on ESD protection devices, the ESD robustness of CMOS ICs can be restored without affecting the operating speed of internal circuits. However, to deposit the sacrificial oxide and to define the selected regions for SB, additional mask and process steps are required. As a result, introducing SB into the CMOS manufacturing processes will increase the fabrication cost. To compromise with the fabrica- tion cost, or owing to the inaccessibility of SB in some given process technologies, some cost-effective ballasting techniques have been proposed to improve the ESD robustness of fully silicided MOSFETs [15]–[28]. In this paper, the mechanism and previous works of bal- lasting techniques on fully silicided MOSFETs are briefly reviewed. Two new ballasting layout schemes are proposed to effectively improve the ESD robustness of input/output (I/O) buffers with fully silicided NMOS and PMOS transistors. Ex- perimental results from real IC products fabricated in a 0.35-μm fully silicided CMOS process have confirmed that the new ballasting layout schemes can successfully increase the human body model (HBM) ESD robustness of fully silicided I/O buffers from the original 1.5 kV to over 6 kV without using the additional SB mask. Moreover, by using the new proposed ballasting layout schemes, no additional layout area of I/O buffers is required, compared to that drawn with the traditional SB technique [17]. II. REVIEW ON BALLASTING TECHNIQUES FOR FULLY SILICIDED I/O BUFFERS Due to the huge discharging current in ESD events, current crowding has been known to cause serious impact on ESD 0018-9383/$26.00 © 2009 IEEE