Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product I-Cheng Lin 1 , Chih-Yao Huang 2 , Chuan-Jane Chao 1 , Ming-Dou Ker * Technology Development Division, Winbond Electronics Corporation, No. 9 Li-Hsin Rd., Science-Based Industrial Park, Hsinchu 300, Taiwan, ROC Received 30 December 2002; received in revised form 14 April 2003 Abstract Latchup failure induced by electrostatic discharge (ESD) protection circuits occurred anomalously in a high-voltage IC product. Latchup issues existed at only three output pins, two of which belonged to the top and the other to the side. The layouts of top and bottom output pins are identical, and side output pins have another identical layouts. In our experiments it was found latchup of two top output pins were originated from the latchup of the side output pin, and therefore heat-induced latchup aggravation issue must be noticed during latchup test. Furthermore, large power line current (Idd) existed during triggering this side output pin and led to subsequent latchup. After thorough layout in- spection, the layout of this side output pin is identical to all other side output pins except that it has an additional N- well (NW) resistor of gate-triggered high-voltage PMOS beside. It was later proved by engineering experiments that this NW resistor is the origin of inducing latchup in this product, and a new mechanism was proposed for this latchup failure. Improvements and solutions were also provided to successfully solve the latchup issues of these three output pins. Ó 2003 Elsevier Ltd. All rights reserved. 1. Introduction Technological advances in ULSI and high-voltage devices have made possible the developments of high- voltage integrated circuits (HVICs). However, with more lightly doped drain junction in order to sustain high enough breakdown voltage, accompanied with higher operating voltage (and resultant high power dis- sipation), the electrical overstress (EOS) is becoming more severe in high-voltage devices and poses serious threat to device reliability, such as electrostatic discharge (ESD) and latchup. In this paper, we present an anomalous latchup fail- ure phenomenon of a HVICs. Of all layout-similar output pins, only three pins showed latchup failure under JEDEC Standard 78 test [1]. In later experiments it was found latchup of the first two pins were induced by the latchup of the third pin. Large power line current (Idd) existed when triggering this third pin and latchup occurred. The large power line current was due to the turning on of high-voltage PMOSs (HVPMOSs) of ESD power clamp circuits, and the HVPMOSs were turned on due to negative-gate-biasing by injected electron flow building up voltage drop across the N-well (NW) resis- tor during the latchup trigger test. Preventing the turn- ing-on of HVPMOSs by focused ion beam (FIB) cutting experiments resolved the large power line currents and subsequent latchup events during JEDEC current trigger test at the same time. Microelectronics Reliability 43 (2003) 1295–1301 www.elsevier.com/locate/microrel * Corresponding author. Address: Integrated Circuits and Systems, Institute of Electronics, National Chiao-Tung Uni- versity, No. 1001, Ta-Hsueh Road, Hsinchu 300, Taiwan, ROC. Tel.: +886-3-571-2121x54173; fax: +886-3-571-5412. E-mail addresses: yclin18@winbond.com.tw (I.-C. Lin, C.-Y. Huang, C.-J. Chao), mdker@ieee.org (M.-D. Ker). 1 Tel.: +886-3-5678168x6219; fax: +886-3-5796038. 2 Present address: Department of Electronic Engineering, Ching-Yun Institute of Technology, 229, Chien-Hsin Road, Jung-Li, Taiwan 320, ROC. Tel.: +886-3-4581196x5119; fax: +886-3-4588924. 0026-2714/$ - see front matter Ó 2003 Elsevier Ltd. All rights reserved. doi:10.1016/S0026-2714(03)00139-2