A 0.13µm CMOS Current Steering D/A Con- verter for PLC and VDSL Applications Jesús Ruiz-Amaya*, J.Francisco Fernández-Bootello, José M. de la Rosa, Manuel Del- gado-Restituto, R. del Río Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC) Edificio CICA-CNM, Avda Reina Mercedes s/n, 41012-Sevilla, SPAIN * ruiz@imse.cnm.es; phone +34955056666; fax +34955056686; www.imse.cnm.es Abstract − This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in a 0.13µm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The converter is segmented in an unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from cur- rent-cell switching matrix core block and distributed in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q 2 Ran- dom-Walk switching sequence. Transistor-level simula- tion results show that the Spurious-Free Dynamic-Range is better than 58.5dB up to 80MS/s. The estimated Sig- nal-to-Noise Distortion Ratio yield is 99.7% and better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher than 59dB for several DMT test sig- nals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm 2 active area. Keywords: digital-to-analog converters, current source, segmentation, switching sequence. I. INTRODUCTION The trend to reduce the cost of market communi- cation devices has motivated the interest for embedded high-speed high-resolution D igital-to-A nalog C on- verters (DAC’s). These converters are essential com- ponents of modern applications such as video signal processing, digital signal synthesis, and both broad- band and wireless communications. Of several archi- tecture alternatives, CMOS current steering DAC’s have demonstrated to be an attractive solution for these applications [1][2][3] because of two reasons mainly: (a) they can be implemented in adverse digital CMOS technology with evident power consumption and inte- grability advantages and (b) they are intrinsically faster and more linear that their counterparts-based on resis- tors or capacitors ladders [4]. However, the combina- tion of high data conversion rate, accuracy and linearity is difficult to achieve. In this paper, dynamic and static limitations for the circuit linearity have been investigated, resulting in the presented DAC and in the development of a behavioural simulator which has aided in its design. Details about this behavioural sim- ulator are beyond of scope of this paper, but more information can be found in [5]. The paper is organized as followed. In Section II, the D/A converter architecture as well as the main design trade-offs are discussed. In Section III, the basic building blocks are presented, namely the current cell, the driver, the level-shifter, the latch and the thermom- eter decoder. Layout issues are explained in Section IV. Finally, transistor-level simulation results are shown in Section V. II. D/A ARCHITECTURE The basic block diagram of a segmented current steering DAC is shown in Fig.1, where the input N-bit are split in b L east S ignificant B its (LSB’s), which steer a binary weigthed array of current sources -binary segment-, and M ost S ignificant B its (MSB’s), which are thermometer-wise decoded to steer an unary array of current sources −thermometer seg- ment. The current sources are commuted on/off by means of complementary switches which are synchro- nized and biased by latches and drivers circuits, respec- tively. In this block diagram it can be distinguished three high-level important factors: the segmentation, i.e. the number of thermometer (t) and binary (b) bits, the switching scheme, that is, the sequence in which the Fig. 1: Block diagram of a segmented current steering DAC. b N b N 1 – … b b 1 + b b b b 1 – … b 1 … … Thermometer decoder Latency equalizer Swatch array (latches+drivers+switches) Current source array Cascode current source t N b – =