A New Time-Based Architecture for Serial Communication Links Mostafa Rashdan, Abdel Yousif, James Haslett and Brent Maundy Department of Electrical and Computer Engineering University of Calgary Calgary, Canada haslett@atips.ca Abstract—A new time-based architecture for serial communication links is presented in this paper. The design is based on a low-power pulse-position modulator (PPM) as a transmitter and a low-power, single-cycle-latency time-to-digital converter (TDC) as a receiver. Using the proposed architecture, a 4 Gbps link over a 40 inch FR4 channel has been designed using a 1 GHz input clock signal and performance is compared with a serializer/deserializer (SerDes) link with the same data rate. The proposed architecture concentrates the transmitted signal energy in a significantly lower bandwidth than the conventional SerDes system at the same data rate. This allows simpler circuitry at the receiver side to recover the transmitted data, using smaller chip area and lower power dissipation. The technique can be readily expanded to modulate both edges of the signal, and the clock can also be embedded to avoid the need for a separate clock line. I. INTRODUCTION In serial data link applications, the SerDes architecture is commonly used in the link design. The architecture is based on a serializer circuit at the transmitter side and a deserializer circuit at the receiver side as shown in figure 1. Figure 1. Block diagram of the conventional SerDes system Inter-Symbol Interference (ISI) effects are a serious problem in these systems due to attenuation and transmission line reflections in the transmission media. A preemphasis circuit at the transmitter side and an equalization circuit at the receiver side are needed in order to compensate the channel effects and recover the transmitted codes successfully. A number of circuits are needed in the design that consume significant power as well as large chip area, including a precise high frequency phase-locked loop (PLL) circuit, a clock and data recovery circuit (CDR), a phase interpolator (PI), a phase detector (PD) and frequency detector circuits (FDs). With increasing data rates, the complexity of the required circuits as well as the power consumption and the chip area are increasing. The clock signal in the transmitter side is not synchronized with the generated clock in the receiver side, requiring clock recovery in the receiver. Clock jitter is also a major problem. It is dominated by power supply and substrate noise, which do not scale with technology [1]. As data rates increase, the performance of multigigabit links will be limited by the clock jitter. A new time-based signaling architecture for serial communication links is proposed in this paper. The architecture is based on a pulse-position modulator (PPM) at the transmitter side and a time-to-digital converter (TDC) at the receiver side. The proposed link does not consume as much chip area, power and bandwidth as the conventional SerDes system, and, to first order avoids the jitter problem that appears in the conventional SerDes system. I. PPM-TDC LINK The proposed link is shown in figure 2. Figure 2. Block diagram of the proposed link The PPM block modulates the positive edges of the clock pulses in time according to the input code and generates the PPM signal. Both the clock signal and the PPM signal are transmitted, so that the TDC can translate the time difference between the positive edges of the clock pulses and the positive edges of the PPM signal pulses into a binary code corresponding to the transmitted data. Since the PPM signal is generated from the clock, the jitter problem does not affect the recovery process in the proposed link, to first order. Any jitter happening to the clock edge will be carried over to the