Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI) A.V-Y. Thean, D. Zhang, V.Vartanian,V. Adams, J. Conner, M. Canonico, H. Desjardin, P. Grudowski, B. Gu, Z.-H. Shi, S. Murphy, G. Spencer, S. Filipiak, D. Goedeke, X-D. Wang, B.Goolsby, V. Dhandapani, L. Prabhu, S. Backer, L-B La, D. Burnett, T. White, B.-Y. Nguyen, B.E.White, S. Venkatesan, J. Mogab, I. Cayrefourcq†, C. Mazure† Freescale Semiconductor Inc., 3501 Ed Bluestein Blvd., MD: K-10, Austin, TX 78721, USA. †SOITEC, Parc technologique des Fontaines, Bernin 38926 Crolles Cedex France Tel: 512-933-2816, Fax: 512-933-6962, Email: Aaron.Thean@freescale.com Abstract This paper describes a biaxial-uniaxial hybridized strained CMOS technology achieved through selective uniaxial relaxation of thick SSOI, dual-stress nitride capping layer, and embedded SiGe source/drain. Through novel strain engineering, nFET/pFET Idsat enhancements as high as 27%/36% have been achieved for sub-40nm devices at 1V with 30% reduction in gate leakage current, while introducing minimum process complexity. This work demonstrates the scalability of SC-SSOI and its advantages over pure biaxial and single uniaxial strained Si technologies. Introduction As mobility enhancement becomes a key enabler of performance scaling for 45- and 32-nm technologies, it has become necessary to develop a scalable strained Si CMOS solution that introduces minimal process complexity and circuit design disruptions. Meanwhile, by offering intrinsically lower leakage and reduced parasitic capacitances, Silicon-On-Insulator (SOI) technologies are becoming better-suited to meet the power-speed demands of high-end portable and embedded electronics. Through the extension of Freescale’s proven partially- depleted HiperMOS SOI architecture, SC-SSOI devices and circuits were recently demonstrated [1]. This paper reports on further enhancement of SC-SSOI performance by integrating the high-strain SOI substrate with process-induced stressors through selective uniaxial relaxation (SUR). This work demonstrates, through novel strain engineering, the compatibility and scalability of thick SSOI CMOS with popular process-induced stressors like dual-stress nitride capping layer (dESL) and embedded SiGe S/D (eSiGe) stressors, while introducing minimal process complexity. nFET Enhancement By providing a high tension directly in the device channel, SSOI can function as a strain platform to attain higher channel stress when combined with process-induced stressors (Fig. 1). As a strain platform, maintaining and controlling strain stability during full CMOS processing is key. Although the intrinsic stress is stable for a continuous super-critically thick strained wafer [1], patterned areas of strained Si formed after shallow-trench isolation (STI) become susceptible to relaxation, due to mechanical interactions between process, SOI thickness, and free-surface relaxation (Fig. 2). Through process design, substantial strain in the smallest devices can be preserved [1] and the device stresses can be selectively manipulated. To appreciate the effects of relaxation, SSOI devices can be deliberately relaxed at the wafer level through specific thermal processing. Figure 3 charts the behavior of the gate current in response to biaxial strain relaxation. To maintain low gate leakage, a 1.5-nm thick SiON gate dielectric has been grown for the devices. Due to the influence of high biaxial strain, the SSOI nFET gate currents are further reduced by 30% relative to the unstrained devices with matched gate oxides [1]. After deliberate strain relief, the SSOI gate current reduction diminishes to only 17% (Fig. 3). This correlates to a 24% low-field mobility reduction due to lower strain, as seen from the change in long n-channel transconductance (Fig. 4). Short channel electron mobility enhancement is evident from the substantial reduction in the gradient (dR tot /dL) of the linear nFET channel resistance (Fig. 5). Electron mobility enhancement due to SSOI with tensile nitride capping layer (tESL) resulted in as much as 38% lower resistance over SOI with the same uniaxial stressor. This translates to 18% and 27% Idsat improvements over uniaxially-strained SOI and unstrained SOI, respectively (Fig. 6). cESL-SSOI pFET Enhancement To achieve the desired strain configuration for enhanced (100)/<110> pFETs, the undesired SSOI tensile strain components have to be selectively removed and replaced by compression [2]. Figure 7 depicts the UV-Raman spectra of identically- sized/shaped nFET and pFET SSOI regions, on the same wafer, subjected to a selective relaxation process. Through engineered implants and thermal processes, as much as 50-60% relaxation of the pFET region (590 MPa) can be induced with minimal impact on nFET stress (1.33 GPa). Furthermore, the crystallinity of the pFET region has been dramatically maintained (indicated by the <10% phonon spectrum broadening relative to pristine Si) (Fig. 7). Phonon spectrum for process B illustrates an example of an un-optimized process that achieved much less pFET relaxation (33%) at the cost of higher crystal degradation (>75% spectrum broadening). SUR, implemented after gate formation, preserves the width- tension (Fig. 8). The compression along the channel is then introduced via a compressive nitride capping layer (cESL). The additional 12% reduction in SUR-SSOI p-channel resistance (Fig. 9) demonstrates the additional hole mobility enhancement due to residual width tension. The improvement led to a 6% Idsat improvement in SUR-SSOI devices over the uniaxially strained SOI and 36% enhancement over unstrained SOI pFETs (Fig. 10). With strong built-in width tension, SUR-SSOI negates the need for STI stressors [3] and further simplifies the process for enhanced CMOS. eSiGe-SSOI pFET Enhancement Figure 11 shows TEM cross-section image of a SSOI pFET with eSiGe. All eSiGe devices in this study were fabricated base on processes reported in Ref. 4. A HRTEM image and crystal diffractogram analysis of the boxed region (Fig. 11) shows the complex interaction of the residual SSOI tension and the compression due to eSiGe (Fig. 12). The lattice diffractogram also mapped the strong residual tension near the buried oxide region away from the eSiGe which has to be relieved in order to enhance the eSiGe effectiveness. Channel resistance data show the dramatic reduction in short-channel hole mobility (20%) when the undesired SSOI stress is relieved (Fig. 13). This resulted in as much as 23% Idsat enhancement over unstrained devices and a slight 4% improvement over uniaxially- strained SOI with eSiGe (Fig. 14). SSOI Wafer Defectivity To achieve large circuit yield, intrinsic high-strain wafer defects inherited from the relaxed SiGe buffer prior to SSOI layer-transfer are of concern. Two categories of defects: isolated threading dislocations (TD’s) (causes junction leakage increase) and extended lateral defects due to pile-ups of TD (PU’s) (causes circuit shorts) are conscientiously reduced (Fig. 15 (Top)). Through extensive process improvements, reduction of PU’s and TD’s has been dramatically accelerated (Fig. 15). It is expected that low-defect SSOI wafers comparable to commercial SOI are upcoming. Conclusion Through a novel method of selective biaxial-uniaxial strain hybridization, this work demonstrates a scalable enhanced SSOI CMOS technology. With this mixed-strain approach, nFET uniaxial strain can be amplified by the substrate strain platform while SSOI pFETs can be enhanced beyond conventional single unaxially-strained or biaxially- strained Si. This is all accomplished with additional gate leakage reduction at minimal process complexity cost. 1-4244-0005-8/06/$20.00 (c) 2006 IEEE 2006 Symposium on VLSI Technology Digest of Technical Papers