Parameter extraction in polysilicon nanowire MOSFETs using new double integration-based procedure A. Ortiz-Conde a, * , A.D. Latorre Rey a , W. Liu b , W.-C. Chen c , H.-C. Lin c , J.J. Liou b,d , J. Muci a , F.J. García-Sánchez a a Solid-State Electronics Laboratory, Simón Bolívar University, Caracas 1080, Venezuela b School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, FL 32816-2450, USA c Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan d Department of ISEE, Zhejiang University, Hangzhou, China article info Article history: Received 7 October 2009 Received in revised form 21 December 2009 Accepted 21 January 2010 Available online 12 February 2010 The review of this paper was arranged by A. Zaslavsky Keywords: Parameter extraction Threshold voltage Subthreshold Slope Double integration Successive integration Polysilicon Nanowire MOSFETs Noise reduction abstract A new double integration-based method to extract model parameters is applied to experimental polysil- icon nanowire MOSFETs. The threshold voltage and Subthreshold Slope factor are extracted from noisy measured current–voltage characteristics. It is shown that the present method offers advantages over previous extraction procedures regarding data noise reduction. In addition, the normalized mutual inte- gral difference operator method is scrutinized and an improvement of the method is presented. Ó 2010 Elsevier Ltd. All rights reserved. 1. Introduction Some of the more promising devices, being considered as possi- ble alternatives to conventional CMOS, are monocrystalline dou- ble- and surrounding-gate MOSFETs [1–5]. At the same time, amorphous silicon (a-Si) thin-film transistors (TFTs) have tradi- tionally dominated display applications, but today there is a grow- ing need for better performance than what a-Si technology can provide. Consequently, polycrystalline silicon (poly-Si) TFTs are also receiving a great deal of attention as alternatives for large- area, low cost displays, as well as for other 3-D and large-area elec- tronics applications. However, the performance of conventional planar poly-Si TFTs is still significantly impaired by the abundance of grain boundary defects in the polysilicon film [6]. These defects disturb carrier transport and particularly give rise to high Sub- threshold Slope factor and off-state leakage current. Many polysilicon MOSFET applications require reducing the amount of defects present in the channel body in order to decrease their harmful impact on the device’s performance. Several technol- ogies have been proposed to increase the polysilicon film grain size. They include excimer laser annealing [7] and metal-induced lateral crystallization [8], among others. An interesting alternative to increasing grain size is to reduce the influence of grain boundaries by significantly shrinking the channel body size. The use of polycrystalline nanowire (NW) chan- nel structures seems to be an appealing course of action towards that objective, since the total number of defects decreases signifi- cantly when the NW cross section is decreased. In that line, several NW polysilicon MOSFETs have been reported [9–14]. Polycrystal- line long-channel ultra-thin body surrounding-gate NW MOSFETs have been proposed and fabricated [15,16] for flexible macroelec- tronics, as well as for other unconventional applications such as highly sensitive biosensors [17,18]. Modeling the phenomenology specific to polysilicon MOSFETs has been a topic of research for the last three decades [19,20]. 0038-1101/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2010.01.011 * Corresponding author. Tel.: +58 212 9064010; fax: +58 212 9064025. E-mail address: ortizc@ieee.org (A. Ortiz-Conde). Solid-State Electronics 54 (2010) 635–641 Contents lists available at ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse