The First International Conference of Electrical, Communication, Computer, Power and Control Engineering ICECCPCE'13/December17-18, 2013 FPGA Implementation of a Modiied Advanced Encryption Standard Algorithm Ali A. Abed Department of Computer Engineering University of Basra, IRAQ aaad bayahoo.com Abstract- In this paper, a method to improve the security level of advanced encryption standard (AES) algorithm is proposed. The proposed algorithm, which is based on the standard AES, increases the complexity of the encryption process leading to a more diicultness against attacking and decryption of the plaintext without using the correct encryption key. The research investigates the AES algorithm with regard to Field Programmable Gate Array (FPGA) and the Very High Speed Integrated Circuit Hardware Description Language (VHDL). ModelSim-Altera Starter Edition Sotware for Quartus II is used for simulation and optimization of the structural VHDL code. All the required transformations of the encryption and decryption processes are done using a pipelined cyclic design method to minimize hardware consumptions. The pipelined design is implemented on Altera Cyclone IV family of FPGA devices and a good throughput is achieved with minimal area. Keywords: Encryption, Decryption, AES, FPGA, VHDL I. INTRODUCTION The National Institute of Standards and Technology (NIST) decided proposals for the AES algorithm. The AES, which is a Federal Infonnation Processing Standard (FIPS), is a cryptographic algorithm implemented to protect elecronic digital data against attacking and it is widely accepted due to its strong encryption, sophisticated processing and its resistance to Brute-force attack [1]. It is a 128-bit symmetric block cipher that can encipher and decipher digital information. Encryption converts data to unintelligible fonnat called cipher text. Decryption of the cipher text leads to retun back data to its original plaintext. The cryptographic key that can be adopted in AES is 128, 192, or 256 bits length [1]. Although key size detennines the level of security, area and power consumption becomes crucial especially in embedded hardware in mobile devices [2]. In this paper, the Rijndael algorithm is adopted since it had the best overall scores in security, performance, eiciency, lexibility, and implementation ability [3]. The hardware implementation of the Rijndael algorithm can provide either high perfonnance or low cost for speciic applications. For some communication systems or servers, it is not favorable to Ali A. Jawad Department of Electrical Power, Technical College, Basra, IRAQ alijwmail.com lose processing speed, which degrades the eiciency of the system during running of the cryptographic algorithm in sotware. Hence, a low cost and small design FPGA cryptographic card will be designed. The trade-off between level of security, throughput and area consumption depends on required need [2]. This card can be used in smart applications allowing a wide range of secure equipment. In spite of the many works on AES and FPGA design of this cryptography algorithm but it can urther improved. In [3], the classical AES is implemented without any modiication. In [4], a modiication in AES is done but it is programmed with MATLAB leading to a non-reduced area logic design. The author of [5] ried to apply the pipeline principle to the classical AES algorithm and implemented it with Virtex FPGA. In this paper, we have done many different facilities with a modiied version of AES. The rest of the paper is organized as follows: Section II is concened with explanation of the encryption process with our proposed modiication. In section III, the decryption process is displayed. Section IV deal with the VHDL sotware implementation of the modiied AES. Section V provides the FPGA hardware implementation of encryption/decryption system. In section VI, the obtained results and veriication are given with some required discussion. Section I summarize the main conclusions. II. ENCRYPTION PROCESS The low chart of this process is illusrated in Figure 1 [3]. It contains a number of ransfomations applied sequentially on a data block in a ixed number of rounds (Nr). This Nr depends on the length of the encryption key. A. Bytes Substitution Transformation Bytesub (state) is a non-linear substitution of bytes that operates independently on each byte of the state using a substitution table (S-Box) [4]. The state is four rows of bytes that the intenal operations of AES are performed on it. The application of the S-Box to each byte of the state is shown in