Integrated circuit transmission-line transformer power combiner for millimetre-wave applications A.M. Niknejad, M. Bohsali, E. Adabi and B. Heydari A new approach for power combining several low-voltage CMOS ampliﬁers using a new on-chip transmission line transformer structure is presented. The power combiner utilises the interconnection of short sections of integrated differential lines and has an efﬁciency indepen- dent of the transformation ratio. Full-wave electromagnetic simulation conﬁrms the operation and low insertion loss of the transformer. Introduction: One of the key challenges to the realisation of a fully integrated CMOS transceiver is the realisation of the power ampliﬁer in a low-voltage CMOS process. The requirements for high-speed operation, namely short channel length and thin gate oxide, are fundamentally at odds with high-power capability, determined in large part by the breakdown voltage of the technology. Two issues limit the output power of CMOS transistors, especially at millimetre (mm)-wave frequencies. For a low-voltage transistor to realise high output power impedance transformation is required in order to trans- form down the antenna impedance to a sufﬁciently low value. In essence, by utilisation of a very large FET, one can deliver power by using a large current instead of voltage. Typical LC resonant matching networks, however, suffer from a trade-off between matching ratio and insertion loss. So there is a practical limit to the output power determined by the losses incurred in the matching network. Recently demonstrated transformer power combining networks [1–3] have the advantage that they can transform the load at constant insertion loss nearly independent of the matching ratio. This is a very important advantage for CMOS technology, which suffers from relatively lossy passive devices owing to the conductive substrate and thin metal layers. Compare the loss of a classic Wilkinson combiner to a transformer- based system. If a corporate ladder structure is employed, the loss increases logarithmically with the number of stages N: P out ¼ g log 2 N NP o where g is the insertion loss of each stage, and P o is the output power of each ampliﬁer. For example, assuming P out =P o ¼ 10 when g ¼ 1dB requires 32 stages with an overall efﬁciency of only 33%. In comparison, a single-stage combining network has an efﬁciency of about 80%. On the other hand, an N-way Wilkinson power combiner suffers high losses so that g N > g, resulting in no net improvement of efﬁciency. In a transformer-based combiner, all the power stages combine simulta- neously and the loss is, to ﬁrst order, only a function of the individual transformer loss, which is typically 1 dB for on-chip optimised structures. Transmission-line balun combiner: In the proposed combiner, each pair of coupled lines forms a transmission-line transformer. At lower frequencies the lines can be realised using coupled inductors. At higher frequencies, however, differential transmission lines are used instead. As shown in Fig. 1, one end of the line is excited in single- ended fashion (although differential drive is possible and preferable), while at the tail end of the line the odd-mode voltages are summed in phase to form a voltage across a balanced or unbalanced load. The purpose of the balun is to convert a signal referenced to ground into a balanced ‘ﬂoating’ voltage. Since a single-ended drive excites both even- and odd-mode waves, it is important to create a line with large even-mode impedance Z oe in order to suppress this unwanted mode. The odd-mode impedance, on the other hand, should equal the source impedance in order to obtain a match. To realise a mm-wave ampliﬁer, each transistor is ﬁrst scaled up as much as feasible in order to obtain sufﬁcient gain. Then N transistors each drive a pair of lines forming a balanced transmission line. The lines are connected at the load so that the load current ﬂows through all structures, whereas the voltages at the tail end of the line sum appropriately. The load of NZ oo is therefore transformed down to an impedance of Z oo . This structure is easily implemented on-chip by placing the tails of the transmission lines in close proximity to allow easy interconnection of the lines. The inputs of the lines are separated to minimise parasitic coupling between the lines. The length of the lines should be kept as small as practical to minimise the line losses. Unlike a conventional balun employing 90  sections, lines as short as 5–10  have been simulated and show good performance. This is important for two reasons: size and hence cost for an integrated balun, and performance (insertion loss). Fig. 1 Transmission-line transformer-based power combining allows low- voltage stages to sum power into a load efﬁciently Fig. 2 Magnitude of coupled power (dB) from four-way power combiner against normalised even-mode impedance; lines excited in differential mode Simulation results: To verify the functionality of this structure, a circuit level simulation was performed. Ideal lines are modelled with Agilent ADS coupled lines. Fig. 2 shows the magnitude of the coupling terms S 5x , where four lines are joined to power combine. Here a relatively short 10  line is employed with varying even-mode impedance. For larger even-mode impedance, the line behaves as desired, approaching perfect power summation (6 dB). To improve the performance of the combiner, a ‘ﬂoating’ differential drive is preferred. In a single-ended drive, impractically large values of Z oe =Z oo are required. In the design of the combiner, the gap spacing is chosen to appropriately fashion the odd-mode impedance Z odd ¼ ﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ L  M C 0 þ 2C c s where L and M are the line self and mutual inductance per unit length, and C 0 and C c are the line-to-ground and line-to-line coupling capaci- tance per unit length. The even-mode impedance is given by Z even ¼ ﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ L þ M C 0 s For good performance, we wish to maximise the ratio of Z even to Z odd : Z even Z odd ¼ ﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ L þ M L  M C 0 þ 2C c C 0 s ELECTRONICS LETTERS 1st March 2007 Vol. 43 No. 5